From f2418d7f5a9734590c4e0d3392886423b2e818a9 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 19 May 2017 16:14:00 +0200 Subject: finish wiring and add eurocard compliant standard holes since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused). --- .../MainBoard PCB ECO 19.05.2017 11-16-39.LOG | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG (limited to 'hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG') diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG new file mode 100644 index 0000000..dbe4382 --- /dev/null +++ b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 11-16-39.LOG @@ -0,0 +1,8 @@ +Added Component: Designator=J2(KLD-0202) +Added Pin To Net: NetName=NetC11_2 Pin=J2-1 +Added Pin To Net: NetName=NetC11_2 Pin=J2-1 +Added Pin To Net: NetName=DB9-5 Pin=J2-2 +Added Pin To Net: NetName=DB9-5 Pin=J2-2 +Added Pin To Net: NetName=NetJ2_3 Pin=J2-3 +Added Pin To Net: NetName=NetJ2_3 Pin=J2-3 +Added Member To Class: ClassName=Peripherals Member=Component J2 PWR2.5 -- cgit v1.2.1