From f2418d7f5a9734590c4e0d3392886423b2e818a9 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 19 May 2017 16:14:00 +0200 Subject: finish wiring and add eurocard compliant standard holes since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused). --- hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-15-57.LOG | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-15-57.LOG (limited to 'hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-15-57.LOG') diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-15-57.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-15-57.LOG new file mode 100644 index 0000000..1b7135b --- /dev/null +++ b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-15-57.LOG @@ -0,0 +1,4 @@ +Added Component: Designator=C24(RB7.6-15) +Added Pin To Net: NetName=NetC11_2 Pin=C24-1 +Added Pin To Net: NetName=DB9-5 Pin=C24-2 +Added Member To Class: ClassName=Peripherals Member=Component C24 Cap Pol1 -- cgit v1.2.1