From f2418d7f5a9734590c4e0d3392886423b2e818a9 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 19 May 2017 16:14:00 +0200 Subject: finish wiring and add eurocard compliant standard holes since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused). --- hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-17-08.LOG | 1 + 1 file changed, 1 insertion(+) create mode 100644 hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-17-08.LOG (limited to 'hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-17-08.LOG') diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-17-08.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-17-08.LOG new file mode 100644 index 0000000..01a0856 --- /dev/null +++ b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 15-17-08.LOG @@ -0,0 +1 @@ +Change Component Footprint: Designator=C24 Old Footprint=RB7.6-15 New Footprint=RB5-10.5 -- cgit v1.2.1