From a952876ae9787d603cf5cf5c19b7f0be34e883f2 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 28 Apr 2017 18:19:42 +0200 Subject: start printed circuit board design wired: - clock circiuts - reset button set layout for: - CPU & memory - serial interface --- hw/Project Logs for z80uPC/MainBoard PCB ECO 26.04.2017 16-27-14.LOG | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 hw/Project Logs for z80uPC/MainBoard PCB ECO 26.04.2017 16-27-14.LOG (limited to 'hw/Project Logs for z80uPC/MainBoard PCB ECO 26.04.2017 16-27-14.LOG') diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 26.04.2017 16-27-14.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 26.04.2017 16-27-14.LOG new file mode 100644 index 0000000..db8ea1a --- /dev/null +++ b/hw/Project Logs for z80uPC/MainBoard PCB ECO 26.04.2017 16-27-14.LOG @@ -0,0 +1,4 @@ +Change Component Footprint: Designator=P3 Old Footprint=MHDR2X5 New Footprint=HDR2X5 +Change Net Name : Old Net Name=GND New Net Name=DB9-5 +Added Member To Class: ClassName=Peripherals Member=Component C10 Cap +Added Room: Name=MainSheet -- cgit v1.2.1