From 9e922f16b26ddf5434d3265d285168bc0858c44c Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Tue, 4 Apr 2017 10:12:37 +0200 Subject: schematic complete hw: change address decoder chip from GAL16V8 to M4-32/32 (CPLD) change main bus connector with a custom one (intead of PC/104) start building footprint library --- .../MainSheet SCH ECO 31.03.2017 14-10-14.LOG | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 hw/Project Logs for z80uPC/MainSheet SCH ECO 31.03.2017 14-10-14.LOG (limited to 'hw/Project Logs for z80uPC/MainSheet SCH ECO 31.03.2017 14-10-14.LOG') diff --git a/hw/Project Logs for z80uPC/MainSheet SCH ECO 31.03.2017 14-10-14.LOG b/hw/Project Logs for z80uPC/MainSheet SCH ECO 31.03.2017 14-10-14.LOG new file mode 100644 index 0000000..9b707c2 --- /dev/null +++ b/hw/Project Logs for z80uPC/MainSheet SCH ECO 31.03.2017 14-10-14.LOG @@ -0,0 +1,6 @@ +Change Component Designator: Old Designator=S? New Designator=S1 +Change Component Designator: Old Designator=U? New Designator=U1 +Change Component Designator: Old Designator=U? New Designator=U2 +Change Component Designator: Old Designator=U? New Designator=U3 +Change Component Designator: Old Designator=U? New Designator=U4 +Change Component Designator: Old Designator=U? New Designator=U5 -- cgit v1.2.1