From a29b4fd588d6f3136bfef0d5dc1ee40ead328b15 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Tue, 23 May 2017 11:51:48 +0200 Subject: board complete, generate gerber (x2) files this is probably the last commit before printing the PCB, unless there are some other errors in the board design --- .../MainBoard PCB ECO 19.05.2017 16-18-01.LOG | 0 .../MainBoard PCB ECO 19.05.2017 16-18-42.LOG | 11 +++++++++++ 2 files changed, 11 insertions(+) create mode 100644 hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-01.LOG create mode 100644 hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-42.LOG (limited to 'hw/Project Logs for z80uPC') diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-01.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-01.LOG new file mode 100644 index 0000000..e69de29 diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-42.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-42.LOG new file mode 100644 index 0000000..3ebc3ad --- /dev/null +++ b/hw/Project Logs for z80uPC/MainBoard PCB ECO 19.05.2017 16-18-42.LOG @@ -0,0 +1,11 @@ +Added Component: Designator=J2(KLD-0202) +Added Pin To Net: NetName=NetC11_2 Pin=J2-1 +Added Pin To Net: NetName=NetC11_2 Pin=J2-1 +Added Pin To Net: NetName=NetC11_2 Pin=J2-1 +Added Pin To Net: NetName=DB9-5 Pin=J2-2 +Added Pin To Net: NetName=DB9-5 Pin=J2-2 +Added Pin To Net: NetName=DB9-5 Pin=J2-2 +Added Pin To Net: NetName=NetJ2_3 Pin=J2-3 +Added Pin To Net: NetName=NetJ2_3 Pin=J2-3 +Added Pin To Net: NetName=NetJ2_3 Pin=J2-3 +Added Member To Class: ClassName=Peripherals Member=Component J2 PWR2.5 -- cgit v1.2.1