From 70b8b7f2d766f4ca131f9fa299546eb3697db8d4 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 23 Mar 2017 20:42:26 +0100 Subject: changed scheme layout hw: changed scheme and annotated components doc: added build script for windows sw: added res/ folder with blaster and created jedec document for address decoder pld --- hw/z80uPC.PrjPCB | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'hw/z80uPC.PrjPCB') diff --git a/hw/z80uPC.PrjPCB b/hw/z80uPC.PrjPCB index 7e07ec3..0395203 100644 --- a/hw/z80uPC.PrjPCB +++ b/hw/z80uPC.PrjPCB @@ -1670,6 +1670,23 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=CRKCRSAN +[Document97] +DocumentPath=Job1.OutJob +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId= + [GeneratedDocument1] DocumentPath=Project Outputs for z80uPC\MainSheet.NET DItemRevisionGUID= @@ -1688,6 +1705,9 @@ Variant=[No Variations] GenerateBOM=1 OutputJobsCount=0 +[Generic_EDE] +OutputDir= + [OutputGroup1] Name=Netlist Outputs Description= -- cgit v1.2.1