From 43be150dc6e84f6f6eeb071cd3cdb7fc21125d60 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Tue, 30 Oct 2018 11:41:24 +0100 Subject: Move sw to sw-old and hw to hw-altium, add kicad files --- sw-old/cpld/address_decoder.log | 46 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100755 sw-old/cpld/address_decoder.log (limited to 'sw-old/cpld/address_decoder.log') diff --git a/sw-old/cpld/address_decoder.log b/sw-old/cpld/address_decoder.log new file mode 100755 index 0000000..cd0a45f --- /dev/null +++ b/sw-old/cpld/address_decoder.log @@ -0,0 +1,46 @@ +|--------------------------------------------| +|- ispDesignExpert Fitter Report File -| +|- Version 8.3.02.12_DE_HDL_BASE -| +|- (c)Copyright, Lattice Semiconductor 1999 -| +|--------------------------------------------| + + + +*** Source file is address_decoder.tt4 . Device is M4-32/32-15JC . + + F35109: For this device, all input pairing is ignored since input + registers or latches do not exist. All signals must pass + through the central switch matrix before being latched or + registered. + F40016: 0 pins have been reserved out of 34 . + F40021: 34 pins are available after reservation, 21 are required + by the design. + F35065: For outputs, implicit output enables will be set to VCC. + +*** End of Pla2db. +Check preplaced pins/nodes +Check preplaced blocks +Check unreferenced pins/nodes +Check clock rules + +List of non-global clocks: + None. + +*** End of Normalization. + +*** End of DRC. + +*** Start Partitioning + +*** Partitioning successful. + + +*** Starting Place&Route + +*** Place&Route Successful +*** The JEDEC file generated is address_decoder.jed . +*** Report Generator invoked. +*** Report Generator end. + +// Fitting successful. +// ERROR count 0 WARNING count 0 . -- cgit v1.2.1