From 43be150dc6e84f6f6eeb071cd3cdb7fc21125d60 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Tue, 30 Oct 2018 11:41:24 +0100
Subject: Move sw to sw-old and hw to hw-altium, add kicad files

---
 sw-old/cpld/address_decoder.tc_ | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100755 sw-old/cpld/address_decoder.tc_

(limited to 'sw-old/cpld/address_decoder.tc_')

diff --git a/sw-old/cpld/address_decoder.tc_ b/sw-old/cpld/address_decoder.tc_
new file mode 100755
index 0000000..0054dc8
--- /dev/null
+++ b/sw-old/cpld/address_decoder.tc_
@@ -0,0 +1,37 @@
+#-- Synplicity, Inc.
+#-- Synplify version 5.3.2
+#-- Project file C:\_prossn\cpld.nao\address_decoder.tc_
+#-- Written on Thu Nov 23 11:54:34 2017
+
+#device options
+set_option -technology mach
+set_option -part MACH111
+
+#add_file options
+add_file -vhdl -lib work "address_decoder.vhd"
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler false
+set_option -resource_sharing true
+
+#map options
+set_option -frequency 0.000
+set_option -fanin_limit 20
+set_option -max_terms_per_macrocell 16
+set_option -map_logic false
+set_option -area_delay_percent 0
+set_option -top_module ADDRESS_DECODER
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint true
+
+#MTI Cross Probe options
+set_option -mti_root ""
+
+#set result format/file last
+project -result_file "address_decoder.edi"
-- 
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