From 985e16b181fd55e28538f2d4524550bd425b86e9 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Thu, 13 Apr 2017 16:03:11 +0200
Subject: switch from GAL (pld) to M4 32/32 CPLD

add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port
---
 sw/cpld/ADDRESS_DECODER.STY | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 sw/cpld/ADDRESS_DECODER.STY

(limited to 'sw/cpld/ADDRESS_DECODER.STY')

diff --git a/sw/cpld/ADDRESS_DECODER.STY b/sw/cpld/ADDRESS_DECODER.STY
new file mode 100644
index 0000000..afd24c5
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.STY
@@ -0,0 +1,4 @@
+[STRATEGY-LIST]
+Normal=True, 1491209776
+[synthesis-type]
+tool=Synplify
-- 
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