From 141137dfe5bdc7400d5cc1ad388b670f9f2e9446 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Thu, 23 Nov 2017 14:34:55 +0100
Subject: update cpld files from VHDL dev machine and delete programmer code
 (unused)

---
 sw/cpld/ADDRESS_DECODER.TCL | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100755 sw/cpld/ADDRESS_DECODER.TCL

(limited to 'sw/cpld/ADDRESS_DECODER.TCL')

diff --git a/sw/cpld/ADDRESS_DECODER.TCL b/sw/cpld/ADDRESS_DECODER.TCL
new file mode 100755
index 0000000..e83cb1f
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.TCL
@@ -0,0 +1,37 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file .\ADDRESS_DECODER.TCL
+#-- Written on Thu Nov 23 11:54:33 2017
+
+
+#-- begin a new section
+project -new
+
+#-- Device options
+set_option -technology mach
+
+#-- add_file options
+add_file -vhdl -lib work "address_decoder.vhd"
+
+#-- top module name
+set_option -top_module ADDRESS_DECODER
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#-- set result format/file last
+project -result_file "ADDRESS_DECODER.edi"
+
+#-- error message log file
+project -log_file ADDRESS_DECODER.log
+
+#-- let's save it
+project -save ADDRESS_DECODER.tc_
+
+#-- run Synplify
+project -run
+
+#-- **************************************************
+
+#-- exit from Synplify
+exit
-- 
cgit v1.2.1