From 985e16b181fd55e28538f2d4524550bd425b86e9 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Thu, 13 Apr 2017 16:03:11 +0200
Subject: switch from GAL (pld) to M4 32/32 CPLD

add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port
---
 sw/cpld/ADDRESS_DECODER.naf | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 sw/cpld/ADDRESS_DECODER.naf

(limited to 'sw/cpld/ADDRESS_DECODER.naf')

diff --git a/sw/cpld/ADDRESS_DECODER.naf b/sw/cpld/ADDRESS_DECODER.naf
new file mode 100644
index 0000000..fe52855
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.naf
@@ -0,0 +1,22 @@
+PA[15]  i
+PA[14]  i
+PA[13]  i
+PA[12]  i
+PA[11]  i
+PA[10]  i
+PA[9]  i
+PA[8]  i
+PA[7]  i
+PA[6]  i
+PA[5]  i
+PA[4]  i
+PA[3]  i
+PA[2]  i
+PA[1]  i
+PA[0]  i
+CSROMH  o
+CSROML  o
+CSRAM  o
+CSUART  o
+CSCTC  o
+CSPIO  o
-- 
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