From 985e16b181fd55e28538f2d4524550bd425b86e9 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Thu, 13 Apr 2017 16:03:11 +0200
Subject: switch from GAL (pld) to M4 32/32 CPLD

add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port
---
 sw/cpld/ADDRESS_DECODER.syn | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 sw/cpld/ADDRESS_DECODER.syn

(limited to 'sw/cpld/ADDRESS_DECODER.syn')

diff --git a/sw/cpld/ADDRESS_DECODER.syn b/sw/cpld/ADDRESS_DECODER.syn
new file mode 100644
index 0000000..419b6ba
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.syn
@@ -0,0 +1,11 @@
+JDF B
+// Created by Version 2.0 
+PROJECT ADDRESS_DECODER
+DESIGN address_decoder Normal
+DEVKIT M4A3-32/32-10JC
+ENTRY Pure VHDL
+MODULE address_decoder.vhd
+MODSTYLE ADDRESS_DECODER Normal
+SYNTHESIS_TOOL Synplify
+SIMULATOR_TOOL ActiveHDL
+TOPMODULE ADDRESS_DECODER
-- 
cgit v1.2.1