From 141137dfe5bdc7400d5cc1ad388b670f9f2e9446 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 23 Nov 2017 14:34:55 +0100 Subject: update cpld files from VHDL dev machine and delete programmer code (unused) --- sw/cpld/address_decoder.bl3 | 52 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100755 sw/cpld/address_decoder.bl3 (limited to 'sw/cpld/address_decoder.bl3') diff --git a/sw/cpld/address_decoder.bl3 b/sw/cpld/address_decoder.bl3 new file mode 100755 index 0000000..70065ad --- /dev/null +++ b/sw/cpld/address_decoder.bl3 @@ -0,0 +1,52 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12 +#$ DATE Thu Nov 23 11:54:43 2017 +#$ MODULE address_decoder +#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ \ +# IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_ CSCTC \ +# CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ +.model address_decoder +.inputs MMU_IN_15_.BLIF IORQ.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF \ +MMU_IN_12_.BLIF MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF \ +MMU_IN_3_.BLIF MMU_IN_2_.BLIF +.outputs MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ \ +MMU_OUT_13_ MMU_OUT_12_ +.names MMU_IN_15_.BLIF MMU_OUT_15_ +1 1 +0 0 +.names MMU_IN_15_.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF CSROML +-1- 1 +1-- 1 +--1 1 +000 0 +.names MMU_IN_15_.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF CSROMH +--0 1 +-1- 1 +1-- 1 +001 0 +.names MMU_IN_15_.BLIF CSRAM +0 1 +1 0 +.names CSUART + 0 +.names CSCTC + 0 +.names IORQ.BLIF MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF \ +MMU_IN_3_.BLIF MMU_IN_2_.BLIF CSPIO +-----1- 1 +----0-- 1 +---1--- 1 +--1---- 1 +-1----- 1 +1------ 1 +------1 1 +0000100 0 +.names MMU_IN_14_.BLIF MMU_OUT_14_ +1 1 +0 0 +.names MMU_IN_13_.BLIF MMU_OUT_13_ +1 1 +0 0 +.names MMU_IN_12_.BLIF MMU_OUT_12_ +1 1 +0 0 +.end -- cgit v1.2.1