From 6105426e159a55cfb15fee3e999bb4fcf6289446 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Fri, 16 Jun 2017 15:25:54 +0200
Subject: new components list and cpld test unit

---
 sw/cpld_test/cpld_test.STY | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 sw/cpld_test/cpld_test.STY

(limited to 'sw/cpld_test/cpld_test.STY')

diff --git a/sw/cpld_test/cpld_test.STY b/sw/cpld_test/cpld_test.STY
new file mode 100644
index 0000000..3b3c6ba
--- /dev/null
+++ b/sw/cpld_test/cpld_test.STY
@@ -0,0 +1,22 @@
+[Normal]
+synlibXRef=lc4k_pvhd, VHDL.TASKLSVhd, 0, Yes
+_EdfFrequency=lc4k_pvhd, VHDL.TASKLSVhd, 0, 200
+_EdfInConsFile=lc4k_pvhd, VHDL.TASKLSVhd, 0,  
+_EdfSymFSM=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfFanin=lc4k_pvhd, VHDL.TASKLSVhd, 0, 20
+_EdfMaxMacrocell=lc4k_pvhd, VHDL.TASKLSVhd, 0, 16
+_EdfPerDesignOptTiming=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0
+_EdfOutputPreFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfMapLogic=lc4k_pvhd, VHDL.TASKLSVhd, 0, False
+_EdfInsertIO=lc4k_pvhd, VHDL.TASKLSVhd, 0, False
+_EdfOutNetForm=lc4k_pvhd, VHDL.TASKLSVhd, 0, None
+_EdfNumCritPath=lc4k_pvhd, VHDL.TASKLSVhd, 0, 3
+_EdfUnconsClk=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfNumStartEnd=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0
+_EdfResSharing=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfPushTirstates=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfDefEnumEncode=lc4k_pvhd, VHDL.TASKLSVhd, 0, default
+_EdfArrangeVHDLFiles=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfSynOnOffImp=lc4k_pvhd, VHDL.TASKLSVhd, 0, False
+[STRATEGY-LIST]
+Normal=True, 1496317751
-- 
cgit v1.2.1

