From 6105426e159a55cfb15fee3e999bb4fcf6289446 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Fri, 16 Jun 2017 15:25:54 +0200
Subject: new components list and cpld test unit

---
 sw/cpld_test/cpld_test.lci | 63 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 sw/cpld_test/cpld_test.lci

(limited to 'sw/cpld_test/cpld_test.lci')

diff --git a/sw/cpld_test/cpld_test.lci b/sw/cpld_test/cpld_test.lci
new file mode 100644
index 0000000..62d7d9d
--- /dev/null
+++ b/sw/cpld_test/cpld_test.lci
@@ -0,0 +1,63 @@
+[Device]
+Family=M4A5;
+PartNumber=M4A5-32/32-10JC;
+Package=44PLCC;
+PartType=M4A5-32/32;
+Speed=-10;
+Operating_condition=COM;
+Status=Production;
+
+[Revision]
+Parent=m4a5.lci;
+DATE=06/01/2017;
+TIME=13:49:11;
+Source_Format=Pure_VHDL;
+Synthesis=Synplify;
+
+[Ignore Assignments]
+
+[Clear Assignments]
+
+[Backannotate Assignments]
+
+[Global Constraints]
+
+[Location Assignments]
+Layer = Off;
+
+[Group Assignments]
+Layer = Off;
+
+[Resource Reservations]
+Layer = Off;
+
+[Fitter Report Format]
+
+[Power]
+
+[Source Constraint Option]
+
+[Fast Bypass]
+
+[OSM Bypass]
+
+[Input Registers]
+
+[Netlist/Delay Format]
+
+[IO Types]
+Layer = off;
+
+[Pullup]
+
+[Slewrate]
+
+[Region]
+
+[Timing Constraints]
+
+[HSI Attributes]
+
+[Input Delay]
+
+
-- 
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