From 6105426e159a55cfb15fee3e999bb4fcf6289446 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Fri, 16 Jun 2017 15:25:54 +0200
Subject: new components list and cpld test unit

---
 sw/cpld_test/cpld_test.prj | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 sw/cpld_test/cpld_test.prj

(limited to 'sw/cpld_test/cpld_test.prj')

diff --git a/sw/cpld_test/cpld_test.prj b/sw/cpld_test/cpld_test.prj
new file mode 100644
index 0000000..eb5548a
--- /dev/null
+++ b/sw/cpld_test/cpld_test.prj
@@ -0,0 +1,34 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj
+#-- Written on Thu Jun 01 13:51:28 2017
+
+
+#device options
+set_option -technology mach
+set_option -part M4A5-32
+
+#compilation/mapping options
+
+#map options
+
+#simulation options
+set_option -write_verilog false
+set_option -write_vhdl false
+
+#timing analysis options
+set_option -synthesis_onoff_pragma false
+
+#-- add_file options
+add_file -vhdl -lib work "cpld_test.vhd"
+
+#-- top module name
+set_option -top_module cpld_test
+
+#-- set result format/file last
+project -result_file "cpld_test.edi"
+
+#-- error message log file
+project -log_file cpld_test.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run
-- 
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