From 6105426e159a55cfb15fee3e999bb4fcf6289446 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Fri, 16 Jun 2017 15:25:54 +0200
Subject: new components list and cpld test unit

---
 sw/cpld_test/cpld_test.syn | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 sw/cpld_test/cpld_test.syn

(limited to 'sw/cpld_test/cpld_test.syn')

diff --git a/sw/cpld_test/cpld_test.syn b/sw/cpld_test/cpld_test.syn
new file mode 100644
index 0000000..06b6554
--- /dev/null
+++ b/sw/cpld_test/cpld_test.syn
@@ -0,0 +1,11 @@
+JDF B
+// Created by Version 2.0 
+PROJECT cpld_test
+DESIGN cpld_test Normal
+DEVKIT M4A5-32/32-10JC
+ENTRY Pure VHDL
+MODULE cpld_test.vhd
+MODSTYLE cpld_test Normal
+SYNTHESIS_TOOL Synplify
+SIMULATOR_TOOL ActiveHDL
+TOPMODULE cpld_test
-- 
cgit v1.2.1