From 141137dfe5bdc7400d5cc1ad388b670f9f2e9446 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 23 Nov 2017 14:34:55 +0100 Subject: update cpld files from VHDL dev machine and delete programmer code (unused) --- sw/cpld_test/.tmp_log | 0 sw/cpld_test/automake.log | 41 -------- sw/cpld_test/cpld_test.STY | 22 ---- sw/cpld_test/cpld_test.htm | 9 -- sw/cpld_test/cpld_test.jhd | 3 - sw/cpld_test/cpld_test.jid | 1 - sw/cpld_test/cpld_test.lci | 63 ------------ sw/cpld_test/cpld_test.lct | 63 ------------ sw/cpld_test/cpld_test.lct.bak | 113 --------------------- sw/cpld_test/cpld_test.naf | 0 sw/cpld_test/cpld_test.prj | 34 ------- sw/cpld_test/cpld_test.rev | 3 - sw/cpld_test/cpld_test.srf | 25 ----- sw/cpld_test/cpld_test.srr | 25 ----- sw/cpld_test/cpld_test.syn | 11 -- sw/cpld_test/cpld_test.vhd | 15 --- sw/cpld_test/cpld_test_tcl.ini | 0 sw/cpld_test/run_options.txt | 56 ---------- sw/cpld_test/scratchproject.prs | 54 ---------- sw/cpld_test/stdout.log | 35 ------- sw/cpld_test/synlog.tcl | 1 - .../synlog/report/cpld_test_compiler_errors.txt | 4 - .../synlog/report/cpld_test_compiler_notes.txt | 3 - .../synlog/report/cpld_test_compiler_runstatus.xml | 41 -------- sw/cpld_test/syntmp/closed.png | Bin 3672 -> 0 bytes sw/cpld_test/syntmp/cmdrec_compiler.log | 7 -- sw/cpld_test/syntmp/cpld_test_srr.htm | 29 ------ sw/cpld_test/syntmp/cpld_test_toc.htm | 25 ----- sw/cpld_test/syntmp/open.png | Bin 452 -> 0 bytes sw/cpld_test/syntmp/run_option.xml | 18 ---- sw/cpld_test/syntmp/statusReport.html | 49 --------- sw/cpld_test/synwork/cpld_test_comp.fdeporig | 22 ---- 32 files changed, 772 deletions(-) delete mode 100644 sw/cpld_test/.tmp_log delete mode 100644 sw/cpld_test/automake.log delete mode 100644 sw/cpld_test/cpld_test.STY delete mode 100644 sw/cpld_test/cpld_test.htm delete mode 100644 sw/cpld_test/cpld_test.jhd delete mode 100644 sw/cpld_test/cpld_test.jid delete mode 100644 sw/cpld_test/cpld_test.lci delete mode 100644 sw/cpld_test/cpld_test.lct delete mode 100644 sw/cpld_test/cpld_test.lct.bak delete mode 100644 sw/cpld_test/cpld_test.naf delete mode 100644 sw/cpld_test/cpld_test.prj delete mode 100644 sw/cpld_test/cpld_test.rev delete mode 100644 sw/cpld_test/cpld_test.srf delete mode 100644 sw/cpld_test/cpld_test.srr delete mode 100644 sw/cpld_test/cpld_test.syn delete mode 100644 sw/cpld_test/cpld_test.vhd delete mode 100644 sw/cpld_test/cpld_test_tcl.ini delete mode 100644 sw/cpld_test/run_options.txt delete mode 100644 sw/cpld_test/scratchproject.prs delete mode 100644 sw/cpld_test/stdout.log delete mode 100644 sw/cpld_test/synlog.tcl delete mode 100644 sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt delete mode 100644 sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt delete mode 100644 sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml delete mode 100644 sw/cpld_test/syntmp/closed.png delete mode 100644 sw/cpld_test/syntmp/cmdrec_compiler.log delete mode 100644 sw/cpld_test/syntmp/cpld_test_srr.htm delete mode 100644 sw/cpld_test/syntmp/cpld_test_toc.htm delete mode 100644 sw/cpld_test/syntmp/open.png delete mode 100644 sw/cpld_test/syntmp/run_option.xml delete mode 100644 sw/cpld_test/syntmp/statusReport.html delete mode 100644 sw/cpld_test/synwork/cpld_test_comp.fdeporig (limited to 'sw/cpld_test') diff --git a/sw/cpld_test/.tmp_log b/sw/cpld_test/.tmp_log deleted file mode 100644 index e69de29..0000000 diff --git a/sw/cpld_test/automake.log b/sw/cpld_test/automake.log deleted file mode 100644 index f33bc75..0000000 --- a/sw/cpld_test/automake.log +++ /dev/null @@ -1,41 +0,0 @@ -ispLEVER Auto-Make Log File ---------------------------- - -Updating: Pre-Fit Equations - -Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\Synpwrap.exe -e cpld_test -target mach -pro ' - -Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. -Version : 2.0.00.17.20.15 - -Done sucessfully with exit code 2. -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] - -Error output EDIF file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi -Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 - -Done: failed with exit code: 0002. diff --git a/sw/cpld_test/cpld_test.STY b/sw/cpld_test/cpld_test.STY deleted file mode 100644 index 3b3c6ba..0000000 --- a/sw/cpld_test/cpld_test.STY +++ /dev/null @@ -1,22 +0,0 @@ -[Normal] -synlibXRef=lc4k_pvhd, VHDL.TASKLSVhd, 0, Yes -_EdfFrequency=lc4k_pvhd, VHDL.TASKLSVhd, 0, 200 -_EdfInConsFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, -_EdfSymFSM=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfFanin=lc4k_pvhd, VHDL.TASKLSVhd, 0, 20 -_EdfMaxMacrocell=lc4k_pvhd, VHDL.TASKLSVhd, 0, 16 -_EdfPerDesignOptTiming=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0 -_EdfOutputPreFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfMapLogic=lc4k_pvhd, VHDL.TASKLSVhd, 0, False -_EdfInsertIO=lc4k_pvhd, VHDL.TASKLSVhd, 0, False -_EdfOutNetForm=lc4k_pvhd, VHDL.TASKLSVhd, 0, None -_EdfNumCritPath=lc4k_pvhd, VHDL.TASKLSVhd, 0, 3 -_EdfUnconsClk=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfNumStartEnd=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0 -_EdfResSharing=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfPushTirstates=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfDefEnumEncode=lc4k_pvhd, VHDL.TASKLSVhd, 0, default -_EdfArrangeVHDLFiles=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfSynOnOffImp=lc4k_pvhd, VHDL.TASKLSVhd, 0, False -[STRATEGY-LIST] -Normal=True, 1496317751 diff --git a/sw/cpld_test/cpld_test.htm b/sw/cpld_test/cpld_test.htm deleted file mode 100644 index 365f96f..0000000 --- a/sw/cpld_test/cpld_test.htm +++ /dev/null @@ -1,9 +0,0 @@ - - - syntmp/cpld_test_srr.htm log file - - - - - - diff --git a/sw/cpld_test/cpld_test.jhd b/sw/cpld_test/cpld_test.jhd deleted file mode 100644 index 9be00a5..0000000 --- a/sw/cpld_test/cpld_test.jhd +++ /dev/null @@ -1,3 +0,0 @@ - - -MODULE cpld_test diff --git a/sw/cpld_test/cpld_test.jid b/sw/cpld_test/cpld_test.jid deleted file mode 100644 index c77ab04..0000000 --- a/sw/cpld_test/cpld_test.jid +++ /dev/null @@ -1 +0,0 @@ -. cpld_test cpld_test.vhd \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd diff --git a/sw/cpld_test/cpld_test.lci b/sw/cpld_test/cpld_test.lci deleted file mode 100644 index 62d7d9d..0000000 --- a/sw/cpld_test/cpld_test.lci +++ /dev/null @@ -1,63 +0,0 @@ -[Device] -Family=M4A5; -PartNumber=M4A5-32/32-10JC; -Package=44PLCC; -PartType=M4A5-32/32; -Speed=-10; -Operating_condition=COM; -Status=Production; - -[Revision] -Parent=m4a5.lci; -DATE=06/01/2017; -TIME=13:49:11; -Source_Format=Pure_VHDL; -Synthesis=Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -Layer = Off; - -[Group Assignments] -Layer = Off; - -[Resource Reservations] -Layer = Off; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] - -[IO Types] -Layer = off; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - - diff --git a/sw/cpld_test/cpld_test.lct b/sw/cpld_test/cpld_test.lct deleted file mode 100644 index 62d7d9d..0000000 --- a/sw/cpld_test/cpld_test.lct +++ /dev/null @@ -1,63 +0,0 @@ -[Device] -Family=M4A5; -PartNumber=M4A5-32/32-10JC; -Package=44PLCC; -PartType=M4A5-32/32; -Speed=-10; -Operating_condition=COM; -Status=Production; - -[Revision] -Parent=m4a5.lci; -DATE=06/01/2017; -TIME=13:49:11; -Source_Format=Pure_VHDL; -Synthesis=Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -Layer = Off; - -[Group Assignments] -Layer = Off; - -[Resource Reservations] -Layer = Off; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] - -[IO Types] -Layer = off; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - - diff --git a/sw/cpld_test/cpld_test.lct.bak b/sw/cpld_test/cpld_test.lct.bak deleted file mode 100644 index 4bdf950..0000000 --- a/sw/cpld_test/cpld_test.lct.bak +++ /dev/null @@ -1,113 +0,0 @@ - -[Device] -Family = lc4k; -PartNumber = LC4064ZE-5UMN64C; -Package = 64ucBGA; -PartType = LC4064ZE; -Speed = -5.8; -Operating_condition = COM; -Status = Production; - -[Revision] -Parent = lc4k64e.lci; -DATE = 2002; -TIME = 0:00:00; -Source_Format = Pure_VHDL; -Synthesis = Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -layer = OFF; - -[Group Assignments] -layer = OFF; - -[Resource Reservations] -layer = OFF; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] -NetList = VHDL; - -[IO Types] -layer = OFF; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - -[opt global constraints list] - -[Explorer User Settings] - -[Pin attributes list] - -[global constraints list] - -[Global Constraints Process Update] - -[pin lock limitation] - -[LOCATION ASSIGNMENTS LIST] - -[RESOURCE RESERVATIONS LIST] - -[individual constraints list] - -[Attributes list setting] - -[Timing Analyzer] - -[PLL Assignments] - -[Dual Function Macrocell] - -[Explorer Results] - -[VHDL synplify constraints] - -[VHDL spectrum constraints] - -[verilog synplify constraints] - -[verilog spectrum constraints] - -[VHDL synplify constraints list] - -[VHDL spectrum constraints list] - -[verilog synplify constraints list] - -[verilog spectrum constraints list] - -[Power Guard] - -[ORP Bypass] - -[Register Powerup] diff --git a/sw/cpld_test/cpld_test.naf b/sw/cpld_test/cpld_test.naf deleted file mode 100644 index e69de29..0000000 diff --git a/sw/cpld_test/cpld_test.prj b/sw/cpld_test/cpld_test.prj deleted file mode 100644 index eb5548a..0000000 --- a/sw/cpld_test/cpld_test.prj +++ /dev/null @@ -1,34 +0,0 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj -#-- Written on Thu Jun 01 13:51:28 2017 - - -#device options -set_option -technology mach -set_option -part M4A5-32 - -#compilation/mapping options - -#map options - -#simulation options -set_option -write_verilog false -set_option -write_vhdl false - -#timing analysis options -set_option -synthesis_onoff_pragma false - -#-- add_file options -add_file -vhdl -lib work "cpld_test.vhd" - -#-- top module name -set_option -top_module cpld_test - -#-- set result format/file last -project -result_file "cpld_test.edi" - -#-- error message log file -project -log_file cpld_test.srf - -#-- run Synplify with 'arrange VHDL file' -project -run diff --git a/sw/cpld_test/cpld_test.rev b/sw/cpld_test/cpld_test.rev deleted file mode 100644 index e8bfb3d..0000000 --- a/sw/cpld_test/cpld_test.rev +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/sw/cpld_test/cpld_test.srf b/sw/cpld_test/cpld_test.srf deleted file mode 100644 index 801fff8..0000000 --- a/sw/cpld_test/cpld_test.srf +++ /dev/null @@ -1,25 +0,0 @@ -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] diff --git a/sw/cpld_test/cpld_test.srr b/sw/cpld_test/cpld_test.srr deleted file mode 100644 index 801fff8..0000000 --- a/sw/cpld_test/cpld_test.srr +++ /dev/null @@ -1,25 +0,0 @@ -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] diff --git a/sw/cpld_test/cpld_test.syn b/sw/cpld_test/cpld_test.syn deleted file mode 100644 index 06b6554..0000000 --- a/sw/cpld_test/cpld_test.syn +++ /dev/null @@ -1,11 +0,0 @@ -JDF B -// Created by Version 2.0 -PROJECT cpld_test -DESIGN cpld_test Normal -DEVKIT M4A5-32/32-10JC -ENTRY Pure VHDL -MODULE cpld_test.vhd -MODSTYLE cpld_test Normal -SYNTHESIS_TOOL Synplify -SIMULATOR_TOOL ActiveHDL -TOPMODULE cpld_test diff --git a/sw/cpld_test/cpld_test.vhd b/sw/cpld_test/cpld_test.vhd deleted file mode 100644 index b1161e9..0000000 --- a/sw/cpld_test/cpld_test.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity cpld_test is - IN_PIN: in std_logic; - OUT_PIN: out std_logic; -end; - -architecture behavioral of cpld_test is -begin - OUT_PIN <= not(IN_PIN); -end behavioral; - diff --git a/sw/cpld_test/cpld_test_tcl.ini b/sw/cpld_test/cpld_test_tcl.ini deleted file mode 100644 index e69de29..0000000 diff --git a/sw/cpld_test/run_options.txt b/sw/cpld_test/run_options.txt deleted file mode 100644 index e4fea81..0000000 --- a/sw/cpld_test/run_options.txt +++ /dev/null @@ -1,56 +0,0 @@ -#-- Synopsys, Inc. -#-- Version I-2014.03LC -#-- Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\run_options.txt -#-- Written on Thu Jun 01 13:51:51 2017 - - -#project files -add_file -vhdl -lib work "./cpld_test.vhd" - - - -#implementation: "cpld_test" -impl -add cpld_test -type fpga - -#device options -set_option -technology mach -set_option -part M4A5-32 -set_option -package "" -set_option -speed_grade "" -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "cpld_test" - -# mapper_options -set_option -frequency 1 -set_option -write_verilog 0 -set_option -write_vhdl 0 -set_option -srs_instrumentation 1 - -# Lattice ispMACH4000 -set_option -maxfanin 20 -set_option -RWCheckOnRam 1 -set_option -maxterms 16 -set_option -areadelay 0 -set_option -disable_io_insertion 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./cpld_test.edi" - -#set log file -set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" -impl -active "cpld_test" diff --git a/sw/cpld_test/scratchproject.prs b/sw/cpld_test/scratchproject.prs deleted file mode 100644 index 9db3bb5..0000000 --- a/sw/cpld_test/scratchproject.prs +++ /dev/null @@ -1,54 +0,0 @@ -#-- Synopsys, Inc. -#-- Version I-2014.03LC -#-- Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\scratchproject.prs - -#project files -add_file -vhdl -lib work "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.vhd" - - - -#implementation: "cpld_test" -impl -add \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test -type fpga - -#device options -set_option -technology mach -set_option -part M4A5-32 -set_option -package "" -set_option -speed_grade "" -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "cpld_test" - -# mapper_options -set_option -frequency 1 -set_option -write_verilog 0 -set_option -write_vhdl 0 -set_option -srs_instrumentation 1 - -# Lattice ispMACH4000 -set_option -maxfanin 20 -set_option -RWCheckOnRam 1 -set_option -maxterms 16 -set_option -areadelay 0 -set_option -disable_io_insertion 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi" - -#set log file -set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" -impl -active "cpld_test" diff --git a/sw/cpld_test/stdout.log b/sw/cpld_test/stdout.log deleted file mode 100644 index 968f5e3..0000000 --- a/sw/cpld_test/stdout.log +++ /dev/null @@ -1,35 +0,0 @@ -Running in Lattice mode - - -Starting: C:\ispLEVER_Classic2\synpbase\bin\mbin\synbatch.exe -Install: C:\ispLEVER_Classic2\synpbase -Date: Thu Jun 01 13:51:51 2017 -Version: I-2014.03LC - -Arguments: -product synplify_pro -batch //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj -ProductType: synplify_pro - - - - - -log file: "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr" - -Running cpld_test|cpld_test - -Running: Compile on cpld_test|cpld_test - -Running: Compile Process on cpld_test|cpld_test - -Running: Compile Input on cpld_test|cpld_test -compiler exited with errors -Job: "compiler" terminated with error status: 2. -See log file: "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr" -Return Code: 2 -Run Time:0h:00m:00s -Copied \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr to \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srf - -exit status=2 - -exit status=2 - diff --git a/sw/cpld_test/synlog.tcl b/sw/cpld_test/synlog.tcl deleted file mode 100644 index 403d18e..0000000 --- a/sw/cpld_test/synlog.tcl +++ /dev/null @@ -1 +0,0 @@ -project -load //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.prj diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt b/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt deleted file mode 100644 index fb62f97..0000000 --- a/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt +++ /dev/null @@ -1,4 +0,0 @@ -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -@E|Parse errors encountered - exiting - diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt b/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt deleted file mode 100644 index 6c7370d..0000000 --- a/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt +++ /dev/null @@ -1,3 +0,0 @@ -@N|Running in 32-bit mode -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns - diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml b/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml deleted file mode 100644 index 937182a..0000000 --- a/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr - Start of Compile - - - Failed - - - - 2 - \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_notes.txt - - - 0 - \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_warnings.txt - - - 3 - \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_errors.txt - - - - - - - 0h:00m:00s - - - - - - - 1496317911 - - - \ No newline at end of file diff --git a/sw/cpld_test/syntmp/closed.png b/sw/cpld_test/syntmp/closed.png deleted file mode 100644 index 0d78634..0000000 Binary files a/sw/cpld_test/syntmp/closed.png and /dev/null differ diff --git a/sw/cpld_test/syntmp/cmdrec_compiler.log b/sw/cpld_test/syntmp/cmdrec_compiler.log deleted file mode 100644 index 24cfe61..0000000 --- a/sw/cpld_test/syntmp/cmdrec_compiler.log +++ /dev/null @@ -1,7 +0,0 @@ -C:\ispLEVER_Classic2\synpbase\bin\c_vhdl.exe -osyn \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synwork\cpld_test_comp.srs -top cpld_test -prodtype synplify_pro -nostructver -dfltencoding sequential -encrypt -pro -dmgen \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -loga \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr -rc:2 success:0 -\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synwork\cpld_test_comp.srs|o|0|0 -\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd|i|1496311903|284 -\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr|o|1496317911|1349 -C:\ispLEVER_Classic2\synpbase\bin64\c_vhdl.exe|i|1401224104|5533184 -C:\ispLEVER_Classic2\synpbase\bin\c_vhdl.exe|i|1401223898|2046976 diff --git a/sw/cpld_test/syntmp/cpld_test_srr.htm b/sw/cpld_test/syntmp/cpld_test_srr.htm deleted file mode 100644 index a234dd1..0000000 --- a/sw/cpld_test/syntmp/cpld_test_srr.htm +++ /dev/null @@ -1,29 +0,0 @@ -
-
-#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
-#install: C:\ispLEVER_Classic2\synpbase
-#OS: Windows 7 6.1
-#Hostname: PC805012
-
-#Implementation: cpld_test
-
-$ Start of Compile
-#Thu Jun 01 13:51:51 2017
-
-Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 32-bit mode 
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
-
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-Top entity isn't set yet!
-@E:CD169 : cpld_test.vhd(7) | Illegal declaration
-@E:CD213 : cpld_test.vhd(13) | Undefined identifier
-2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd
-@END
-@E: :  | Parse errors encountered - exiting 
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jun 01 13:51:51 2017
-
-###########################################################]
-
-
diff --git a/sw/cpld_test/syntmp/cpld_test_toc.htm b/sw/cpld_test/syntmp/cpld_test_toc.htm deleted file mode 100644 index 6e8aa83..0000000 --- a/sw/cpld_test/syntmp/cpld_test_toc.htm +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/sw/cpld_test/syntmp/open.png b/sw/cpld_test/syntmp/open.png deleted file mode 100644 index a227005..0000000 Binary files a/sw/cpld_test/syntmp/open.png and /dev/null differ diff --git a/sw/cpld_test/syntmp/run_option.xml b/sw/cpld_test/syntmp/run_option.xml deleted file mode 100644 index 365c522..0000000 --- a/sw/cpld_test/syntmp/run_option.xml +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - diff --git a/sw/cpld_test/syntmp/statusReport.html b/sw/cpld_test/syntmp/statusReport.html deleted file mode 100644 index 1914c86..0000000 --- a/sw/cpld_test/syntmp/statusReport.html +++ /dev/null @@ -1,49 +0,0 @@ - - - - Project Status Summary Page - - - - - - -
- - - - - - - -
Project Settings
Project Name cpld_test Implementation Name cpld_test
Top Module cpld_test Resource Sharing 1
Disable I/O Insertion 0 FSM Compiler 1

- - - - - - - - - - - - - - - - - - - - - - - - - - - -
Run Status
Job NameStatusCPU TimeReal TimeMemoryDate/Time
Compile InputError203-0m:00s-01.06.2017
13:51:51
Map & Optimizeout-of-date0m:00s
-
- \ No newline at end of file diff --git a/sw/cpld_test/synwork/cpld_test_comp.fdeporig b/sw/cpld_test/synwork/cpld_test_comp.fdeporig deleted file mode 100644 index b63dfe0..0000000 --- a/sw/cpld_test/synwork/cpld_test_comp.fdeporig +++ /dev/null @@ -1,22 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-top|cpld_test|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\bin\\c_vhdl.exe":1401223898 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\location.map":1310457374 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\std.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\std1164.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\numeric.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\arith.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722 -#CUR:"\\\\nas001\\account_pif\\_prossn\\samb_3\\lab3\\projects\\z80upc\\sw\\cpld_test\\cpld_test.vhd":1496311903 -0 "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work cpld_test behavioral 0 -- cgit v1.2.1