From 985e16b181fd55e28538f2d4524550bd425b86e9 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Thu, 13 Apr 2017 16:03:11 +0200
Subject: switch from GAL (pld) to M4 32/32 CPLD

add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port
---
 sw/pld/ADDRESS_DECODER.sim | 50 ----------------------------------------------
 1 file changed, 50 deletions(-)
 delete mode 100644 sw/pld/ADDRESS_DECODER.sim

(limited to 'sw/pld/ADDRESS_DECODER.sim')

diff --git a/sw/pld/ADDRESS_DECODER.sim b/sw/pld/ADDRESS_DECODER.sim
deleted file mode 100644
index 05661c0..0000000
--- a/sw/pld/ADDRESS_DECODER.sim
+++ /dev/null
@@ -1,50 +0,0 @@
-%SIGNAL
-PIN   2 =  A8 
-PIN   3 =  A9 
-PIN   4 =  A10 
-PIN   5 =  A11 
-PIN   6 =  A12 
-PIN   7 =  A13 
-PIN   8 =  A14 
-PIN   9 =  A15 
-PIN  16 =  CSCTC 
-PIN  17 =  CSPIO 
-PIN  14 =  CSRAM 
-PIN  13 =  CSROMH 
-PIN  12 =  CSROML 
-PIN  15 =  CSUART 
-%END
-
-%FIELD
-%END
-
-%EQUATION
-CSCTC =>
-    !A8 & A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15
-
-CSPIO =>
-    A8 & A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15
-
-CSRAM =>
-    !A15
-
-CSROMH =>
-    A13 & !A14 & !A15
-
-CSROML =>
-    !A13 & !A14 & !A15
-
-CSTIMER =>
-    A15
-  # A14
-  # !A13
-  # A12
-  # A11
-  # A10
-  # A9
-  # !A8
-
-CSUART =>
-    !A8 & !A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15
-
-%END
-- 
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