From 8b240f0f90cd11f49947cf335a1e366bbe84b3f1 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Tue, 14 Nov 2017 11:46:31 +0100 Subject: Improvements in PIO driver, pio test rewritten in inline asm --- sw/z80/drivers/include/pio.h | 11 +++++++---- sw/z80/drivers/include/usart.h | 4 ++-- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'sw/z80/drivers/include') diff --git a/sw/z80/drivers/include/pio.h b/sw/z80/drivers/include/pio.h index a1137e4..e234b05 100644 --- a/sw/z80/drivers/include/pio.h +++ b/sw/z80/drivers/include/pio.h @@ -4,6 +4,9 @@ #include "addresses.h" #include +// DEBUG +#define PIO_ASM_INTERFACE + // ports #define PIO_A 0 #define PIO_B 1 @@ -12,10 +15,10 @@ #define PIO_REG_DATA 0 #define PIO_REG_CTRL 2 -// #define PIO_REG_DATA_A (PIO_A + PIO_REG_PORT) -// #define PIO_REG_DATA_B 1 (PIO_B + PIO_REG_PORT) -// #define PIO_REG_CTRL_A 2 (PIO_A + PIO_REG_CTRL) -// #define PIO_REG_CTRL_B 3 (PIO_B + PIO_REG_CTRL) +#define PIO_REG_DATA_A (PIO_A | PIO_REG_PORT) +#define PIO_REG_DATA_B 1 (PIO_B | PIO_REG_PORT) +#define PIO_REG_CTRL_A 2 (PIO_A | PIO_REG_CTRL) +#define PIO_REG_CTRL_B 3 (PIO_B | PIO_REG_CTRL) #define PIO_MODE_BYTE_OUT 0 // mode 0 #define PIO_MODE_BYTE_IN 1 // mode 1 diff --git a/sw/z80/drivers/include/usart.h b/sw/z80/drivers/include/usart.h index fdc01e2..05aeb4a 100644 --- a/sw/z80/drivers/include/usart.h +++ b/sw/z80/drivers/include/usart.h @@ -6,7 +6,7 @@ #include #include -// baudrate clock divisors +// baudrate clock divisors // values from TL16C550C datasheet (table 9 for 1.8432 MHz crystal) #define USART_BAUDRATE_50 2304 #define USART_BAUDRATE_75 1536 @@ -125,7 +125,7 @@ struct MSR volatile uint data_carrier_detect :1; }; -/* this structure is only for internal usage */ +/* this structure is only for internal use */ struct _usart_device { register_t buffer; // also used as LSB for divisor latch -- cgit v1.2.1