#PLAFILE address_decoder.tt4
#DATE    09/25/2017
#DESIGN  <no design name>
#DEVICE  mach432

DATA LOCATION CSCTC:B_12_28	// OUT
DATA LOCATION CSPIO:B_8_29	// OUT
DATA LOCATION CSRAM:B_13_26	// OUT
DATA LOCATION CSROMH:B_10_25	// OUT
DATA LOCATION CSROML:B_14_24	// OUT
DATA LOCATION CSUART:B_9_27	// OUT
DATA LOCATION IORQ:B_*_30	// INP
DATA LOCATION MMU_IN_12_:A_*_18	// INP
DATA LOCATION MMU_IN_13_:A_*_19	// INP
DATA LOCATION MMU_IN_14_:A_*_20	// INP
DATA LOCATION MMU_IN_15_:A_*_21	// INP
DATA LOCATION MMU_IN_2_:A_*_7	// INP
DATA LOCATION MMU_IN_3_:A_*_6	// INP
DATA LOCATION MMU_IN_4_:A_*_5	// INP
DATA LOCATION MMU_IN_5_:A_*_4	// INP
DATA LOCATION MMU_IN_6_:A_*_3	// INP
DATA LOCATION MMU_IN_7_:A_*_2	// INP
DATA LOCATION MMU_OUT_12_:B_0_39	// OUT
DATA LOCATION MMU_OUT_13_:B_4_38	// OUT
DATA LOCATION MMU_OUT_14_:B_1_37	// OUT
DATA LOCATION MMU_OUT_15_:B_5_36	// OUT
DATA IO_DIR   CSCTC:OUT
DATA IO_DIR   CSPIO:OUT
DATA IO_DIR   CSRAM:OUT
DATA IO_DIR   CSROMH:OUT
DATA IO_DIR   CSROML:OUT
DATA IO_DIR   CSUART:OUT
DATA IO_DIR   IORQ:IN
DATA IO_DIR   MMU_IN_12_:IN
DATA IO_DIR   MMU_IN_13_:IN
DATA IO_DIR   MMU_IN_14_:IN
DATA IO_DIR   MMU_IN_15_:IN
DATA IO_DIR   MMU_IN_2_:IN
DATA IO_DIR   MMU_IN_3_:IN
DATA IO_DIR   MMU_IN_4_:IN
DATA IO_DIR   MMU_IN_5_:IN
DATA IO_DIR   MMU_IN_6_:IN
DATA IO_DIR   MMU_IN_7_:IN
DATA IO_DIR   MMU_OUT_12_:OUT
DATA IO_DIR   MMU_OUT_13_:OUT
DATA IO_DIR   MMU_OUT_14_:OUT
DATA IO_DIR   MMU_OUT_15_:OUT
DATA PW_LEVEL  MMU_IN_7_:0
DATA SLEW      MMU_IN_7_:0
DATA PW_LEVEL  MMU_IN_6_:0
DATA SLEW      MMU_IN_6_:0
DATA PW_LEVEL  MMU_IN_15_:0
DATA SLEW      MMU_IN_15_:0
DATA PW_LEVEL  MMU_IN_5_:0
DATA SLEW      MMU_IN_5_:0
DATA PW_LEVEL  MMU_IN_4_:0
DATA SLEW      MMU_IN_4_:0
DATA PW_LEVEL  MMU_OUT_15_:0
DATA SLEW      MMU_OUT_15_:0
DATA PW_LEVEL  MMU_IN_3_:0
DATA SLEW      MMU_IN_3_:0
DATA PW_LEVEL  IORQ:0
DATA SLEW      IORQ:0
DATA PW_LEVEL  MMU_IN_2_:0
DATA SLEW      MMU_IN_2_:0
DATA PW_LEVEL  CSROML:0
DATA SLEW      CSROML:0
DATA PW_LEVEL  CSROMH:0
DATA SLEW      CSROMH:0
DATA PW_LEVEL  MMU_OUT_14_:0
DATA SLEW      MMU_OUT_14_:0
DATA PW_LEVEL  CSRAM:0
DATA SLEW      CSRAM:0
DATA PW_LEVEL  MMU_OUT_13_:0
DATA SLEW      MMU_OUT_13_:0
DATA PW_LEVEL  CSUART:0
DATA SLEW      CSUART:0
DATA PW_LEVEL  MMU_OUT_12_:0
DATA SLEW      MMU_OUT_12_:0
DATA PW_LEVEL  CSCTC:0
DATA SLEW      CSCTC:0
DATA PW_LEVEL  CSPIO:0
DATA SLEW      CSPIO:0
DATA PW_LEVEL  MMU_IN_14_:0
DATA SLEW      MMU_IN_14_:0
DATA PW_LEVEL  MMU_IN_13_:0
DATA SLEW      MMU_IN_13_:0
DATA PW_LEVEL  MMU_IN_12_:0
DATA SLEW      MMU_IN_12_:0
END