#$ TOOL ispDesignEXPERT 8.3.02.12
#$ DATE Thu Nov 23 11:54:43 2017
#$ MODULE address_decoder
#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ \
#  IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_ CSCTC \
#  CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_
.model address_decoder
.inputs MMU_IN_15_.BLIF IORQ.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF \
MMU_IN_12_.BLIF MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF \
MMU_IN_3_.BLIF MMU_IN_2_.BLIF
.outputs MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ \
MMU_OUT_13_ MMU_OUT_12_
.names MMU_IN_15_.BLIF MMU_OUT_15_
1 1
0 0
.names MMU_IN_15_.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF CSROML
-1- 1
1-- 1
--1 1
000 0
.names MMU_IN_15_.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF CSROMH
--0 1
-1- 1
1-- 1
001 0
.names MMU_IN_15_.BLIF CSRAM
0 1
1 0
.names CSUART
 0
.names CSCTC
 0
.names IORQ.BLIF MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF \
MMU_IN_3_.BLIF MMU_IN_2_.BLIF CSPIO
-----1- 1
----0-- 1
---1--- 1
--1---- 1
-1----- 1
1------ 1
------1 1
0000100 0
.names MMU_IN_14_.BLIF MMU_OUT_14_
1 1
0 0
.names MMU_IN_13_.BLIF MMU_OUT_13_
1 1
0 0
.names MMU_IN_12_.BLIF MMU_OUT_12_
1 1
0 0
.end