MODELDATA
MODELDATA_VERSION "1.0";
DESIGN "address_decoder";
DATE "Mon Nov 13 11:47:14 2017";
VENDOR "Lattice Semiconductor Co. Ltd.";
PROGRAM "STAMP Model Generator";

/* port drive, max transition and max capacitance */
PORTDATA
MMU_IN_2: MAXTRANS(0.0);
MMU_IN_3: MAXTRANS(0.0);
MMU_IN_4: MAXTRANS(0.0);
MMU_IN_5: MAXTRANS(0.0);
MMU_IN_6: MAXTRANS(0.0);
MMU_IN_7: MAXTRANS(0.0);
MMU_IN_8: MAXTRANS(0.0);
MMU_IN_9: MAXTRANS(0.0);
MMU_IN_10: MAXTRANS(0.0);
MMU_IN_11: MAXTRANS(0.0);
MMU_IN_12: MAXTRANS(0.0);
MMU_IN_13: MAXTRANS(0.0);
MMU_IN_14: MAXTRANS(0.0);
MMU_IN_15: MAXTRANS(0.0);
CSCTC: MAXTRANS(0.0);
CSPIO: MAXTRANS(0.0);
CSRAM: MAXTRANS(0.0);
CSROMH: MAXTRANS(0.0);
CSROML: MAXTRANS(0.0);
CSUART: MAXTRANS(0.0);
MMU_OUT_12: MAXTRANS(0.0);
MMU_OUT_13: MAXTRANS(0.0);
MMU_OUT_14: MAXTRANS(0.0);
MMU_OUT_15: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
MMU_IN_2_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_3_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_4_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_5_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_6_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_7_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_8_CSCTC_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_8_CSPIO_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_8_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_9_CSCTC_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_9_CSPIO_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_9_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_10_CSCTC_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_10_CSPIO_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_10_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_11_CSCTC_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_11_CSPIO_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_11_CSUART_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_12_CSCTC_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ARCDATA
MMU_IN_12_CSPIO_delay:
CELL_RISE(scalar) {
VALUES(15.0);
}
CELL_FALL(scalar) {
VALUES(15.0);
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA