Design Name = address_decoder.tt4
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*******************
* TIMING ANALYSIS *
*******************

Timing Analysis KEY:
One unit of delay time is equivalent to one pass 
     through the Central Switch Matrix.
..   Delay ( in this column ) not applicable to the indicated signal.
TSU, Set-Up Time ( 0 for input-paired signals ),
     represents the number of switch matrix passes between
     an input pin and a register setup before clock.
     TSU is reported on the register.
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
     represents the number of switch matrix passes between
     a clocked register and an output pin.
     TCO is reported on the register.
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
     represents the number of switch matrix passes between
     an input pin and an output pin.
     TPD is reported on the output pin.
TCR, Clocked Output-to-Register Time,
     represents the number of switch matrix passes between
     a clocked register and the register it drives ( before clock ).
     TCR is reported on the driving register.

                    TSU       TCO       TPD       TCR
                  #passes   #passes   #passes   #passes
SIGNAL NAME       min  max  min  max  min  max  min  max
     MMU_OUT_15_  ..   ..   ..   ..    1    1   ..   ..   
          CSROML  ..   ..   ..   ..    1    1   ..   ..   
          CSROMH  ..   ..   ..   ..    1    1   ..   ..   
     MMU_OUT_14_  ..   ..   ..   ..    1    1   ..   ..   
           CSRAM  ..   ..   ..   ..    1    1   ..   ..   
     MMU_OUT_13_  ..   ..   ..   ..    1    1   ..   ..   
     MMU_OUT_12_  ..   ..   ..   ..    1    1   ..   ..   
           CSPIO  ..   ..   ..   ..    1    1   ..   ..