#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj
#-- Written on Thu Jun 01 13:51:28 2017


#device options
set_option -technology mach
set_option -part M4A5-32

#compilation/mapping options

#map options

#simulation options
set_option -write_verilog false
set_option -write_vhdl false

#timing analysis options
set_option -synthesis_onoff_pragma false

#-- add_file options
add_file -vhdl -lib work "cpld_test.vhd"

#-- top module name
set_option -top_module cpld_test

#-- set result format/file last
project -result_file "cpld_test.edi"

#-- error message log file
project -log_file cpld_test.srf

#-- run Synplify with 'arrange VHDL file'
project -run