Rule Violations |
Count |
Board Clearance Constraint (Gap=0mm) (All) |
18 |
Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
Clearance Constraint (Gap=0.15mm) (All),(All) |
0 |
Width Constraint (Min=0.152mm) (Max=1.524mm) (Preferred=0.254mm) (All) |
0 |
Power Plane Connect Rule(Relief Connect )(Expansion=0.175mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All) |
0 |
Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
Un-Routed Net Constraint ( (All) ) |
0 |
Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45))) |
0 |
Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45))) |
0 |
Component Clearance Constraint ( Horizontal Gap = 0.25mm, Vertical Gap = 0.25mm ) (All),(All) |
0 |
Hole Size Constraint (Min=0.25mm) (Max=2mm) (All) |
10 |
Pads and Vias to follow the Drill pairs settings |
0 |
Height Constraint (Min=0mm) (Max=25mm) (Prefered=12.5mm) (All) |
0 |
Hole To Hole Clearance (Gap=0.35mm) (All),(All) |
0 |
Minimum Solder Mask Sliver (Gap=0.08mm) (All),(All) |
0 |
Silk To Solder Mask (Clearance=0.2mm) (IsPad),(All) |
9 |
Silk to Silk (Clearance=0.2mm) (All),(All) |
0 |
Net Antennae (Tolerance=0mm) (All) |
0 |
Power Plane Connect Rule(NoConnect Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) ((ObjectKind = 'Pad') and (Name Like '*DEC*')) |
0 |
Total |
37 |