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[Device]
Family = lc4k;
PartNumber = LC4064ZE-5UMN64C;
Package = 64ucBGA;
PartType = LC4064ZE;
Speed = -5.8;
Operating_condition = COM;
Status = Production;

[Revision]
Parent = lc4k64e.lci;
DATE = 2002;
TIME = 0:00:00;
Source_Format = Pure_VHDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]
NetList = VHDL;

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Power Guard]

[ORP Bypass]

[Register Powerup]