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authorNao Pross <naopross@thearcway.org>2018-03-13 09:54:04 +0100
committerNao Pross <naopross@thearcway.org>2018-03-13 09:54:04 +0100
commit9a95d5ae694325f3655aefb06be2aa28aa9c45f8 (patch)
tree6d5369619c7247bc435fa0927a36f3e15f44c77b /src
parentAdd doc from submodule (diff)
downloadXilofono-9a95d5ae694325f3655aefb06be2aa28aa9c45f8.tar.gz
Xilofono-9a95d5ae694325f3655aefb06be2aa28aa9c45f8.zip
Move comments for printability
Diffstat (limited to 'src')
-rw-r--r--src/main.c116
1 files changed, 77 insertions, 39 deletions
diff --git a/src/main.c b/src/main.c
index 9b5fd28..013da52 100644
--- a/src/main.c
+++ b/src/main.c
@@ -14,64 +14,102 @@
// 'C' source line config statements
// CONFIG1H
-#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block)
-#pragma config PLLCFG = ON // 4X PLL Enable (Oscillator multiplied by 4)
-#pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
-#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
-#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
+// Oscillator Selection bits (Internal oscillator block)
+#pragma config FOSC = INTIO67
+// 4X PLL Enable (Oscillator multiplied by 4)
+#pragma config PLLCFG = ON
+// Primary clock enable bit (Primary clock is always enabled)
+#pragma config PRICLKEN = ON
+// Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
+#pragma config FCMEN = OFF
+// Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
+#pragma config IESO = OFF
// CONFIG2L
-#pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
-#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
-#pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
+// Power-up Timer Enable bit (Power up timer disabled)
+#pragma config PWRTEN = OFF
+// Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
+#pragma config BOREN = SBORDIS
+// Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
+#pragma config BORV = 190
// CONFIG2H
-#pragma config WDTEN = OFF // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
-#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
+// Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
+#pragma config WDTEN = OFF
+// Watchdog Timer Postscale Select bits (1:32768)
+#pragma config WDTPS = 32768
// CONFIG3H
-#pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
-#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
-#pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
-#pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
-#pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0)
-#pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2)
-#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
+// CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
+#pragma config CCP2MX = PORTC1
+// PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
+#pragma config PBADEN = ON
+// P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
+#pragma config CCP3MX = PORTB5
+// HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
+#pragma config HFOFST = ON
+// Timer3 Clock input mux bit (T3CKI is on RC0)
+#pragma config T3CMX = PORTC0
+// ECCP2 B output mux bit (P2B is on RD2)
+#pragma config P2BMX = PORTD2
+// MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
+#pragma config MCLRE = EXTMCLR
// CONFIG4L
-#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
-#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
-#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
+// Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
+#pragma config STVREN = ON
+// Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
+#pragma config LVP = ON
+// Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
+#pragma config XINST = OFF
// CONFIG5L
-#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
-#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
-#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
-#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
+// Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
+#pragma config CP0 = OFF
+// Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
+#pragma config CP1 = OFF
+// Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
+#pragma config CP2 = OFF
+// Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
+#pragma config CP3 = OFF
// CONFIG5H
-#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
-#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
+// Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
+#pragma config CPB = OFF
+// Data EEPROM Code Protection bit (Data EEPROM not code-protected)
+#pragma config CPD = OFF
// CONFIG6L
-#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
-#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
-#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
-#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
+// Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
+#pragma config WRT0 = OFF
+// Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
+#pragma config WRT1 = OFF
+// Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
+#pragma config WRT2 = OFF
+// Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
+#pragma config WRT3 = OFF
// CONFIG6H
-#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
-#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
-#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
+// Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
+#pragma config WRTC = OFF
+// Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
+#pragma config WRTB = OFF
+// Data EEPROM Write Protection bit (Data EEPROM not write-protected)
+#pragma config WRTD = OFF
// CONFIG7L
-#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
-#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
-#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
-#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
+// Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
+#pragma config EBTR0 = OFF
+// Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
+#pragma config EBTR1 = OFF
+// Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
+#pragma config EBTR2 = OFF
+// Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
+#pragma config EBTR3 = OFF
// CONFIG7H
-#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
+// Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
+#pragma config EBTRB = OFF
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
@@ -295,4 +333,4 @@ int eusart_write_midi(const midi_message_t *pkt)
}
return 0;
-} \ No newline at end of file
+}