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Diffstat (limited to 'hw/Project Outputs for Steps/Design Rule Check - Steps.drc')
| -rw-r--r-- | hw/Project Outputs for Steps/Design Rule Check - Steps.drc | 286 |
1 files changed, 286 insertions, 0 deletions
diff --git a/hw/Project Outputs for Steps/Design Rule Check - Steps.drc b/hw/Project Outputs for Steps/Design Rule Check - Steps.drc new file mode 100644 index 0000000..ccf2b9a --- /dev/null +++ b/hw/Project Outputs for Steps/Design Rule Check - Steps.drc @@ -0,0 +1,286 @@ +Protel Design System Design Rule Check +PCB File : Z:\SAMB_4\projects\xilofono\hw\Steps.PcbDoc +Date : 02.02.2018 +Time : 12:09:52 + +Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All) + Violation between Clearance Constraint: (Collision < 0.254mm) Between Track (374.65mm,24.13mm)(377.19mm,26.67mm) on Bottom Layer And Pad J1-1(374.65mm,24.13mm) on Multi-Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Track (377.19mm,26.67mm)(377.19mm,29.21mm) on Bottom Layer And Pad TP5-1(377.19mm,29.21mm) on Multi-Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Track (377.19mm,29.21mm)(378.968mm,30.988mm) on Bottom Layer And Track (377.19mm,26.67mm)(377.19mm,29.21mm) on Bottom Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Track (364.49mm,41.91mm)(377.19mm,29.21mm) on Bottom Layer And Track (377.19mm,26.67mm)(377.19mm,29.21mm) on Bottom Layer +Rule Violations :4 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) + Violation between Short-Circuit Constraint: Between Track (374.65mm,24.13mm)(377.19mm,26.67mm) on Bottom Layer And Pad J1-1(374.65mm,24.13mm) on Multi-Layer Location : [X = 374.96mm][Y = 24.44mm] + Violation between Short-Circuit Constraint: Between Track (377.19mm,26.67mm)(377.19mm,29.21mm) on Bottom Layer And Pad TP5-1(377.19mm,29.21mm) on Multi-Layer Location : [X = 377.19mm][Y = 28.9mm] + Violation between Short-Circuit Constraint: Between Track (377.19mm,29.21mm)(378.968mm,30.988mm) on Bottom Layer And Track (377.19mm,26.67mm)(377.19mm,29.21mm) on Bottom Layer Location : [X = 377.19mm][Y = 29.21mm] + Violation between Short-Circuit Constraint: Between Track (364.49mm,41.91mm)(377.19mm,29.21mm) on Bottom Layer And Track (377.19mm,26.67mm)(377.19mm,29.21mm) on Bottom Layer Location : [X = 377.19mm][Y = 29.21mm] +Rule Violations :4 + +Processing Rule : Un-Routed Net Constraint ( (All) ) + Violation between Un-Routed Net Constraint: Net NetR5_1 Between Pad R5-1(201.422mm,34.544mm) on Multi-Layer And Pad TP10-1(307.34mm,33.02mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net NetP4_4 Between Pad P4-4(231.826mm,31.953mm) on Multi-Layer And Track (439.344mm,25.349mm)(439.42mm,25.425mm) on Top Layer + Violation between Un-Routed Net Constraint: Net PZ23 Between Pad P2-8(323.85mm,21.59mm) on Multi-Layer And Pad U1-9(344.17mm,44.45mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net PZ22 Between Pad P2-7(323.85mm,19.05mm) on Multi-Layer And Pad U1-8(346.71mm,44.45mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net PZ17 Between Pad P2-2(316.23mm,21.59mm) on Multi-Layer And Pad U1-20(316.23mm,44.45mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net VCC Between Pad R4-2(231.902mm,45.974mm) on Multi-Layer And Pad D1_PZ1-2(245.86mm,54.61mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P2-11(328.93mm,19.05mm) on Multi-Layer And Pad P2-12(328.93mm,21.59mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P2-11(328.93mm,19.05mm) on Multi-Layer And Pad P2-13(331.47mm,19.05mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ4-1(280.67mm,72.39mm) on Multi-Layer And Pad Y1_PZ4-2(280.67mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ7-1(322.58mm,72.39mm) on Multi-Layer And Pad Y1_PZ7-2(322.58mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ1-1(238.76mm,72.39mm) on Multi-Layer And Pad Y1_PZ1-2(238.76mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ3-1(266.7mm,72.39mm) on Multi-Layer And Pad Y1_PZ3-2(266.7mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ5-1(294.64mm,72.39mm) on Multi-Layer And Pad Y1_PZ5-2(294.64mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ2-1(252.73mm,72.39mm) on Multi-Layer And Pad Y1_PZ2-2(252.73mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ12-1(392.43mm,72.39mm) on Multi-Layer And Pad Y1_PZ12-2(392.43mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ10-1(364.49mm,72.39mm) on Multi-Layer And Pad Y1_PZ10-2(364.49mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ9-1(350.52mm,72.39mm) on Multi-Layer And Pad Y1_PZ9-2(350.52mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ6-1(308.61mm,72.39mm) on Multi-Layer And Pad Y1_PZ6-2(308.61mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ8-1(336.55mm,72.39mm) on Multi-Layer And Pad Y1_PZ8-2(336.55mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ15-1(434.34mm,72.39mm) on Multi-Layer And Pad Y1_PZ15-2(434.34mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ13-1(406.4mm,72.39mm) on Multi-Layer And Pad Y1_PZ13-2(406.4mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ14-1(420.37mm,72.39mm) on Multi-Layer And Pad Y1_PZ14-2(420.37mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2_PZ11-1(378.46mm,72.39mm) on Multi-Layer And Pad Y1_PZ11-2(378.46mm,78.74mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D1-2(400.05mm,17.78mm) on Multi-Layer And Pad S1-3(405.13mm,20.32mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad C1-2(339.09mm,24.13mm) on Multi-Layer And Pad U1-31(341.63mm,29.21mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P1-2(417.75mm,13.97mm) on Multi-Layer And Pad TP2-1(419.1mm,20.32mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad C1-2(339.09mm,24.13mm) on Multi-Layer And Pad U2-7(349.25mm,24.13mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ4-1(280.67mm,60.325mm) on Multi-Layer And Pad R2_PZ4-1(280.67mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ7-1(322.58mm,60.325mm) on Multi-Layer And Pad R2_PZ7-1(322.58mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ6-1(308.61mm,60.325mm) on Multi-Layer And Pad R2_PZ6-1(308.61mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ5-1(294.64mm,60.325mm) on Multi-Layer And Pad R2_PZ5-1(294.64mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ3-1(266.7mm,60.325mm) on Multi-Layer And Pad R2_PZ3-1(266.7mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ1-1(238.76mm,60.325mm) on Multi-Layer And Pad R2_PZ1-1(238.76mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ15-1(434.34mm,60.325mm) on Multi-Layer And Pad R2_PZ15-1(434.34mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ2-1(252.73mm,60.325mm) on Multi-Layer And Pad R2_PZ2-1(252.73mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ8-1(336.55mm,60.325mm) on Multi-Layer And Pad R2_PZ8-1(336.55mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ12-1(392.43mm,60.325mm) on Multi-Layer And Pad R2_PZ12-1(392.43mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ14-1(420.37mm,60.325mm) on Multi-Layer And Pad R2_PZ14-1(420.37mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ9-1(350.52mm,60.325mm) on Multi-Layer And Pad R2_PZ9-1(350.52mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ10-1(364.49mm,60.325mm) on Multi-Layer And Pad R2_PZ10-1(364.49mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ13-1(406.4mm,60.325mm) on Multi-Layer And Pad R2_PZ13-1(406.4mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ11-1(378.46mm,60.325mm) on Multi-Layer And Pad R2_PZ11-1(378.46mm,72.39mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P4-2(226.822mm,29.464mm) on Multi-Layer And Pad P4-7(229.324mm,19.456mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad J1-3(377.19mm,24.13mm) on Multi-Layer And Pad R2-1(391.16mm,24.13mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad U1-12(336.55mm,44.45mm) on Multi-Layer And Pad D2_PZ8-1(336.55mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P3-4(306.07mm,19.05mm) on Multi-Layer And Pad P2-11(328.93mm,19.05mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P2-13(331.47mm,19.05mm) on Multi-Layer And Pad C1-2(339.09mm,24.13mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ10-1(364.49mm,60.325mm) on Multi-Layer And Pad D2_PZ11-1(378.46mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ12-1(392.43mm,60.325mm) on Multi-Layer And Pad D2_PZ13-1(406.4mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ8-1(336.55mm,60.325mm) on Multi-Layer And Pad D2_PZ9-1(350.52mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ13-1(406.4mm,60.325mm) on Multi-Layer And Pad D2_PZ14-1(420.37mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad S1-3(405.13mm,20.32mm) on Multi-Layer And Pad TP2-1(419.1mm,20.32mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ2-1(252.73mm,60.325mm) on Multi-Layer And Pad D2_PZ3-1(266.7mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ14-1(420.37mm,60.325mm) on Multi-Layer And Pad D2_PZ15-1(434.34mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ1-1(238.76mm,60.325mm) on Multi-Layer And Pad D2_PZ2-1(252.73mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ4-1(280.67mm,60.325mm) on Multi-Layer And Pad D2_PZ5-1(294.64mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ5-1(294.64mm,60.325mm) on Multi-Layer And Pad D2_PZ6-1(308.61mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ6-1(308.61mm,60.325mm) on Multi-Layer And Pad D2_PZ7-1(322.58mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad R2-1(391.16mm,24.13mm) on Multi-Layer And Pad D1-2(400.05mm,17.78mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad P4-2(226.822mm,29.464mm) on Multi-Layer And Pad D2_PZ1-1(238.76mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ11-1(378.46mm,60.325mm) on Multi-Layer And Pad D2_PZ12-1(392.43mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ7-1(322.58mm,60.325mm) on Multi-Layer And Pad D2_PZ8-1(336.55mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ3-1(266.7mm,60.325mm) on Multi-Layer And Pad D2_PZ4-1(280.67mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad U1-12(336.55mm,44.45mm) on Multi-Layer And Pad U1-31(341.63mm,29.21mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad U2-7(349.25mm,24.13mm) on Multi-Layer And Pad J1-3(377.19mm,24.13mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net GND Between Pad D2_PZ9-1(350.52mm,60.325mm) on Multi-Layer And Pad D2_PZ10-1(364.49mm,60.325mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net NetR3_2 Between Pad U2-4(356.87mm,24.13mm) on Multi-Layer And Pad U2-1(364.49mm,24.13mm) on Multi-Layer + Violation between Un-Routed Net Constraint: Net M\C\L\R\ Between Pad J1-1(374.65mm,24.13mm) on Multi-Layer And Pad TP5-1(377.19mm,29.21mm) on Multi-Layer +Rule Violations :68 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.254mm) (Max=1.524mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=10mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (216.662mm,32.512mm)(236.982mm,32.512mm) on Top Overlay And Pad P4-4(231.826mm,31.953mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (216.662mm,32.512mm)(236.982mm,32.512mm) on Top Overlay And Pad P4-5(221.818mm,31.953mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (216.662mm,29.464mm)(236.982mm,29.464mm) on Top Overlay And Pad P4-1(234.328mm,29.464mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (216.662mm,29.464mm)(236.982mm,29.464mm) on Top Overlay And Pad P4-3(219.316mm,29.464mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Track (216.662mm,29.464mm)(236.982mm,29.464mm) on Top Overlay And Pad P4-2(226.822mm,29.464mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (231.902mm,36.83mm)(231.902mm,37.846mm) on Top Overlay And Pad R4-1(231.902mm,35.814mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (231.902mm,43.942mm)(231.902mm,44.958mm) on Top Overlay And Pad R4-2(231.902mm,45.974mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (202.438mm,34.544mm)(203.454mm,34.544mm) on Top Overlay And Pad R5-1(201.422mm,34.544mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (209.55mm,34.544mm)(210.566mm,34.544mm) on Top Overlay And Pad R5-2(211.582mm,34.544mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (442.468mm,72.39mm)(443.484mm,72.39mm) on Top Overlay And Pad R2_PZ15-2(444.5mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (435.356mm,72.39mm)(436.372mm,72.39mm) on Top Overlay And Pad R2_PZ15-1(434.34mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (442.468mm,66.04mm)(443.484mm,66.04mm) on Top Overlay And Pad R1_PZ15-2(444.5mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (435.356mm,66.04mm)(436.372mm,66.04mm) on Top Overlay And Pad R1_PZ15-1(434.34mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (428.498mm,72.39mm)(429.514mm,72.39mm) on Top Overlay And Pad R2_PZ14-2(430.53mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (421.386mm,72.39mm)(422.402mm,72.39mm) on Top Overlay And Pad R2_PZ14-1(420.37mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (428.498mm,66.04mm)(429.514mm,66.04mm) on Top Overlay And Pad R1_PZ14-2(430.53mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (421.386mm,66.04mm)(422.402mm,66.04mm) on Top Overlay And Pad R1_PZ14-1(420.37mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (414.528mm,72.39mm)(415.544mm,72.39mm) on Top Overlay And Pad R2_PZ13-2(416.56mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (407.416mm,72.39mm)(408.432mm,72.39mm) on Top Overlay And Pad R2_PZ13-1(406.4mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (414.528mm,66.04mm)(415.544mm,66.04mm) on Top Overlay And Pad R1_PZ13-2(416.56mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (407.416mm,66.04mm)(408.432mm,66.04mm) on Top Overlay And Pad R1_PZ13-1(406.4mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (400.558mm,72.39mm)(401.574mm,72.39mm) on Top Overlay And Pad R2_PZ12-2(402.59mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (393.446mm,72.39mm)(394.462mm,72.39mm) on Top Overlay And Pad R2_PZ12-1(392.43mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (400.558mm,66.04mm)(401.574mm,66.04mm) on Top Overlay And Pad R1_PZ12-2(402.59mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (393.446mm,66.04mm)(394.462mm,66.04mm) on Top Overlay And Pad R1_PZ12-1(392.43mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (386.588mm,72.39mm)(387.604mm,72.39mm) on Top Overlay And Pad R2_PZ11-2(388.62mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (379.476mm,72.39mm)(380.492mm,72.39mm) on Top Overlay And Pad R2_PZ11-1(378.46mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (386.588mm,66.04mm)(387.604mm,66.04mm) on Top Overlay And Pad R1_PZ11-2(388.62mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (379.476mm,66.04mm)(380.492mm,66.04mm) on Top Overlay And Pad R1_PZ11-1(378.46mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (302.768mm,72.39mm)(303.784mm,72.39mm) on Top Overlay And Pad R2_PZ5-2(304.8mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (295.656mm,72.39mm)(296.672mm,72.39mm) on Top Overlay And Pad R2_PZ5-1(294.64mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (302.768mm,66.04mm)(303.784mm,66.04mm) on Top Overlay And Pad R1_PZ5-2(304.8mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (295.656mm,66.04mm)(296.672mm,66.04mm) on Top Overlay And Pad R1_PZ5-1(294.64mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (316.738mm,72.39mm)(317.754mm,72.39mm) on Top Overlay And Pad R2_PZ6-2(318.77mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (309.626mm,72.39mm)(310.642mm,72.39mm) on Top Overlay And Pad R2_PZ6-1(308.61mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (316.738mm,66.04mm)(317.754mm,66.04mm) on Top Overlay And Pad R1_PZ6-2(318.77mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (309.626mm,66.04mm)(310.642mm,66.04mm) on Top Overlay And Pad R1_PZ6-1(308.61mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (330.708mm,72.39mm)(331.724mm,72.39mm) on Top Overlay And Pad R2_PZ7-2(332.74mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (323.596mm,72.39mm)(324.612mm,72.39mm) on Top Overlay And Pad R2_PZ7-1(322.58mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (330.708mm,66.04mm)(331.724mm,66.04mm) on Top Overlay And Pad R1_PZ7-2(332.74mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (323.596mm,66.04mm)(324.612mm,66.04mm) on Top Overlay And Pad R1_PZ7-1(322.58mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (344.678mm,72.39mm)(345.694mm,72.39mm) on Top Overlay And Pad R2_PZ8-2(346.71mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (337.566mm,72.39mm)(338.582mm,72.39mm) on Top Overlay And Pad R2_PZ8-1(336.55mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (344.678mm,66.04mm)(345.694mm,66.04mm) on Top Overlay And Pad R1_PZ8-2(346.71mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (337.566mm,66.04mm)(338.582mm,66.04mm) on Top Overlay And Pad R1_PZ8-1(336.55mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (358.648mm,72.39mm)(359.664mm,72.39mm) on Top Overlay And Pad R2_PZ9-2(360.68mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (351.536mm,72.39mm)(352.552mm,72.39mm) on Top Overlay And Pad R2_PZ9-1(350.52mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (358.648mm,66.04mm)(359.664mm,66.04mm) on Top Overlay And Pad R1_PZ9-2(360.68mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (351.536mm,66.04mm)(352.552mm,66.04mm) on Top Overlay And Pad R1_PZ9-1(350.52mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (246.888mm,72.39mm)(247.904mm,72.39mm) on Top Overlay And Pad R2_PZ1-2(248.92mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (239.776mm,72.39mm)(240.792mm,72.39mm) on Top Overlay And Pad R2_PZ1-1(238.76mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (246.888mm,66.04mm)(247.904mm,66.04mm) on Top Overlay And Pad R1_PZ1-2(248.92mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (239.776mm,66.04mm)(240.792mm,66.04mm) on Top Overlay And Pad R1_PZ1-1(238.76mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (260.858mm,72.39mm)(261.874mm,72.39mm) on Top Overlay And Pad R2_PZ2-2(262.89mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (253.746mm,72.39mm)(254.762mm,72.39mm) on Top Overlay And Pad R2_PZ2-1(252.73mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (260.858mm,66.04mm)(261.874mm,66.04mm) on Top Overlay And Pad R1_PZ2-2(262.89mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (253.746mm,66.04mm)(254.762mm,66.04mm) on Top Overlay And Pad R1_PZ2-1(252.73mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (274.828mm,72.39mm)(275.844mm,72.39mm) on Top Overlay And Pad R2_PZ3-2(276.86mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (267.716mm,72.39mm)(268.732mm,72.39mm) on Top Overlay And Pad R2_PZ3-1(266.7mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (274.828mm,66.04mm)(275.844mm,66.04mm) on Top Overlay And Pad R1_PZ3-2(276.86mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (267.716mm,66.04mm)(268.732mm,66.04mm) on Top Overlay And Pad R1_PZ3-1(266.7mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (288.798mm,72.39mm)(289.814mm,72.39mm) on Top Overlay And Pad R2_PZ4-2(290.83mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (281.686mm,72.39mm)(282.702mm,72.39mm) on Top Overlay And Pad R2_PZ4-1(280.67mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (288.798mm,66.04mm)(289.814mm,66.04mm) on Top Overlay And Pad R1_PZ4-2(290.83mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (281.686mm,66.04mm)(282.702mm,66.04mm) on Top Overlay And Pad R1_PZ4-1(280.67mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (372.618mm,72.39mm)(373.634mm,72.39mm) on Top Overlay And Pad R2_PZ10-2(374.65mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (365.506mm,72.39mm)(366.522mm,72.39mm) on Top Overlay And Pad R2_PZ10-1(364.49mm,72.39mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (372.618mm,66.04mm)(373.634mm,66.04mm) on Top Overlay And Pad R1_PZ10-2(374.65mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (365.506mm,66.04mm)(366.522mm,66.04mm) on Top Overlay And Pad R1_PZ10-1(364.49mm,66.04mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (394.97mm,22.098mm)(394.97mm,23.114mm) on Top Overlay And Pad R3-1(394.97mm,24.13mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (394.97mm,14.986mm)(394.97mm,16.002mm) on Top Overlay And Pad R3-2(394.97mm,13.97mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (391.16mm,22.098mm)(391.16mm,23.114mm) on Top Overlay And Pad R2-1(391.16mm,24.13mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (391.16mm,14.986mm)(391.16mm,16.002mm) on Top Overlay And Pad R2-2(391.16mm,13.97mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (387.35mm,22.098mm)(387.35mm,23.114mm) on Top Overlay And Pad R1-1(387.35mm,24.13mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.216mm < 0.254mm) Between Track (387.35mm,14.986mm)(387.35mm,16.002mm) on Top Overlay And Pad R1-2(387.35mm,13.97mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.216mm] +Rule Violations :75 + +Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) + Violation between Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "15" (335.534mm,18.542mm) on Top Overlay And Track (335.28mm,17.78mm)(335.28mm,22.86mm) on Top Overlay Silk Text to Silk Clearance [0.052mm] + Violation between Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "16" (335.534mm,21.082mm) on Top Overlay And Track (335.28mm,17.78mm)(335.28mm,22.86mm) on Top Overlay Silk Text to Silk Clearance [0.052mm] + Violation between Silk To Silk Clearance Constraint: (0.222mm < 0.254mm) Between Text "2" (313.69mm,21.082mm) on Top Overlay And Track (314.96mm,17.78mm)(314.96mm,22.86mm) on Top Overlay Silk Text to Silk Clearance [0.222mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ15" (434.975mm,80.645mm) on Top Overlay And Track (438.15mm,77.47mm)(438.15mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ15" (434.975mm,80.645mm) on Top Overlay And Track (433.07mm,80.01mm)(438.15mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ14" (421.005mm,80.645mm) on Top Overlay And Track (424.18mm,77.47mm)(424.18mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ14" (421.005mm,80.645mm) on Top Overlay And Track (419.1mm,80.01mm)(424.18mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ13" (407.035mm,80.645mm) on Top Overlay And Track (410.21mm,77.47mm)(410.21mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ13" (407.035mm,80.645mm) on Top Overlay And Track (405.13mm,80.01mm)(410.21mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ12" (393.065mm,80.645mm) on Top Overlay And Track (396.24mm,77.47mm)(396.24mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ12" (393.065mm,80.645mm) on Top Overlay And Track (391.16mm,80.01mm)(396.24mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ11" (379.095mm,80.645mm) on Top Overlay And Track (382.27mm,77.47mm)(382.27mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ11" (379.095mm,80.645mm) on Top Overlay And Track (377.19mm,80.01mm)(382.27mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ5" (295.275mm,80.645mm) on Top Overlay And Track (298.45mm,77.47mm)(298.45mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ5" (295.275mm,80.645mm) on Top Overlay And Track (293.37mm,80.01mm)(298.45mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ6" (309.245mm,80.645mm) on Top Overlay And Track (312.42mm,77.47mm)(312.42mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ6" (309.245mm,80.645mm) on Top Overlay And Track (307.34mm,80.01mm)(312.42mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ7" (323.215mm,80.645mm) on Top Overlay And Track (326.39mm,77.47mm)(326.39mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ7" (323.215mm,80.645mm) on Top Overlay And Track (321.31mm,80.01mm)(326.39mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ8" (337.185mm,80.645mm) on Top Overlay And Track (340.36mm,77.47mm)(340.36mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ8" (337.185mm,80.645mm) on Top Overlay And Track (335.28mm,80.01mm)(340.36mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ9" (351.155mm,80.645mm) on Top Overlay And Track (354.33mm,77.47mm)(354.33mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ9" (351.155mm,80.645mm) on Top Overlay And Track (349.25mm,80.01mm)(354.33mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ1" (239.395mm,80.645mm) on Top Overlay And Track (242.57mm,77.47mm)(242.57mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ1" (239.395mm,80.645mm) on Top Overlay And Track (237.49mm,80.01mm)(242.57mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ2" (253.365mm,80.645mm) on Top Overlay And Track (256.54mm,77.47mm)(256.54mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ2" (253.365mm,80.645mm) on Top Overlay And Track (251.46mm,80.01mm)(256.54mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ3" (267.335mm,80.645mm) on Top Overlay And Track (270.51mm,77.47mm)(270.51mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ3" (267.335mm,80.645mm) on Top Overlay And Track (265.43mm,80.01mm)(270.51mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ4" (281.305mm,80.645mm) on Top Overlay And Track (284.48mm,77.47mm)(284.48mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ4" (281.305mm,80.645mm) on Top Overlay And Track (279.4mm,80.01mm)(284.48mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ10" (365.125mm,80.645mm) on Top Overlay And Track (368.3mm,77.47mm)(368.3mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.154mm < 0.254mm) Between Text "Y1_PZ10" (365.125mm,80.645mm) on Top Overlay And Track (363.22mm,80.01mm)(368.3mm,80.01mm) on Top Overlay Silk Text to Silk Clearance [0.154mm] + Violation between Silk To Silk Clearance Constraint: (0.189mm < 0.254mm) Between Text "+" (399.473mm,22.72mm) on Top Overlay And Track (398.78mm,21.59mm)(401.32mm,21.59mm) on Top Overlay Silk Text to Silk Clearance [0.189mm] +Rule Violations :34 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) + Violation between Net Antennae: Track (439.344mm,25.349mm)(439.42mm,25.425mm) on Top Layer + Violation between Net Antennae: Track (439.344mm,25.349mm)(439.42mm,25.425mm) on Top Layer +Rule Violations :2 + +Processing Rule : Room PZ9 (Bounding Region = (348.234mm, 52.07mm, 361.95mm, 82.55mm) (InComponentClass('PZ9')) +Rule Violations :0 + +Processing Rule : Room PZ10 (Bounding Region = (362.204mm, 52.07mm, 375.92mm, 82.55mm) (InComponentClass('PZ10')) +Rule Violations :0 + +Processing Rule : Room PZ8 (Bounding Region = (334.264mm, 52.07mm, 347.98mm, 82.55mm) (InComponentClass('PZ8')) +Rule Violations :0 + +Processing Rule : Room PZ7 (Bounding Region = (320.294mm, 52.07mm, 334.01mm, 82.55mm) (InComponentClass('PZ7')) +Rule Violations :0 + +Processing Rule : Room PZ11 (Bounding Region = (376.174mm, 52.07mm, 389.89mm, 82.55mm) (InComponentClass('PZ11')) +Rule Violations :0 + +Processing Rule : Room PZ13 (Bounding Region = (404.114mm, 52.07mm, 417.83mm, 82.55mm) (InComponentClass('PZ13')) +Rule Violations :0 + +Processing Rule : Room PZ14 (Bounding Region = (418.084mm, 52.07mm, 431.8mm, 82.55mm) (InComponentClass('PZ14')) +Rule Violations :0 + +Processing Rule : Room PZ12 (Bounding Region = (390.144mm, 52.07mm, 403.86mm, 82.55mm) (InComponentClass('PZ12')) +Rule Violations :0 + +Processing Rule : Room PZ15 (Bounding Region = (432.054mm, 52.07mm, 445.77mm, 82.55mm) (InComponentClass('PZ15')) +Rule Violations :0 + +Processing Rule : Room PZ2 (Bounding Region = (250.444mm, 52.07mm, 264.16mm, 82.55mm) (InComponentClass('PZ2')) +Rule Violations :0 + +Processing Rule : Room PZ1 (Bounding Region = (236.474mm, 52.07mm, 250.19mm, 82.55mm) (InComponentClass('PZ1')) +Rule Violations :0 + +Processing Rule : Room Steps (Bounding Region = (294.64mm, 6.35mm, 445.77mm, 45.72mm) (InComponentClass('Steps')) + Violation between Room Definition: Between Small Component R5-Res2 (206.502mm,34.544mm) on Top Layer And Room Steps (Bounding Region = (294.64mm, 6.35mm, 445.77mm, 45.72mm) (InComponentClass('Steps')) + Violation between Room Definition: Between Small Component R4-Res2 (231.902mm,40.894mm) on Top Layer And Room Steps (Bounding Region = (294.64mm, 6.35mm, 445.77mm, 45.72mm) (InComponentClass('Steps')) + Violation between Room Definition: Between Component P4-57PC5FS (226.822mm,24.46mm) on Top Layer And Room Steps (Bounding Region = (294.64mm, 6.35mm, 445.77mm, 45.72mm) (InComponentClass('Steps')) +Rule Violations :3 + +Processing Rule : Room PZ3 (Bounding Region = (264.414mm, 52.07mm, 278.13mm, 82.55mm) (InComponentClass('PZ3')) +Rule Violations :0 + +Processing Rule : Room PZ6 (Bounding Region = (306.324mm, 52.07mm, 320.04mm, 82.55mm) (InComponentClass('PZ6')) +Rule Violations :0 + +Processing Rule : Room PZ5 (Bounding Region = (292.354mm, 52.07mm, 306.07mm, 82.55mm) (InComponentClass('PZ5')) +Rule Violations :0 + +Processing Rule : Room PZ4 (Bounding Region = (278.384mm, 52.07mm, 292.1mm, 82.55mm) (InComponentClass('PZ4')) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 190 +Waived Violations : 0 +Time Elapsed : 00:00:02
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