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-rw-r--r--src/dist/default/debug/src.debug.sdb520
1 files changed, 0 insertions, 520 deletions
diff --git a/src/dist/default/debug/src.debug.sdb b/src/dist/default/debug/src.debug.sdb
deleted file mode 100644
index cf91952..0000000
--- a/src/dist/default/debug/src.debug.sdb
+++ /dev/null
@@ -1,520 +0,0 @@
-[p LITE_MODE AUTOSTATIC LFSROK EMI_WORD ]
-[d version 1.1 ]
-[d edition pro ]
-[d chip 18F45K22 ]
-[d frameptr 4065 ]
-"237 Z:\SAMB_4\projects\xilofono\src\main.c
-[e E43 . `uc
-C 0
-D 1
-E 2
-F 3
-G 4
-A 5
-B 6
-]
-"41 Z:\SAMB_4\projects\xilofono\src\midi.c
-[e E40 . `uc
-NOTE_ON 8
-NOTE_OFF 9
-POLYPHONIC_KEYPRESS 10
-CONTROLLER 11
-PROGRAM_CHANGE 12
-CHANNEL_PRESSURE 13
-PITCH_BLEND 15
-]
-"63
-[e E31 . `uc
-C 0
-D 1
-E 2
-F 3
-G 4
-A 5
-B 6
-]
-"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\float.c
-[v ___ftpack __ftpack `(f 1 e 3 0 ]
-"86 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftadd.c
-[v ___ftadd __ftadd `(f 1 e 3 0 ]
-"54 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftdiv.c
-[v ___ftdiv __ftdiv `(f 1 e 3 0 ]
-"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftmul.c
-[v ___ftmul __ftmul `(f 1 e 3 0 ]
-"20 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftsub.c
-[v ___ftsub __ftsub `(f 1 e 3 0 ]
-"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c
-[v _memset memset `(*.39v 1 e 2 0 ]
-"10 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcadd.c
-[v ___fladd __fladd `(d 1 e 3 0 ]
-"245
-[v ___flsub __flsub `(d 1 e 3 0 ]
-"11 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcdiv.c
-[v ___fldiv __fldiv `(d 1 e 3 0 ]
-"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcmul.c
-[v ___flmul __flmul `(d 1 e 3 0 ]
-"15 C:\Program Files\Microchip\xc8\v1.44\sources\common\Umul32.c
-[v ___lmul __lmul `(ul 1 e 4 0 ]
-"114 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _isr isr `II(v 1 e 1 0 ]
-"155
-[v _init_hw init_hw `T(v 1 e 1 0 ]
-"220
-[v _main main `(v 1 e 1 0 ]
-"266
-[v _eusart_write_midi eusart_write_midi `(i 1 e 2 0 ]
-"40 Z:\SAMB_4\projects\xilofono\src\midi.c
-[v _midi_set_status midi_set_status `(i 1 e 2 0 ]
-"51
-[v _midi_set_channel midi_set_channel `(i 1 e 2 0 ]
-"62
-[v _midi_note_on midi_note_on `(i 1 e 2 0 ]
-"4 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _eusart1_init eusart1_init `(v 1 e 1 0 ]
-"25
-[v _eusart2_init eusart2_init `(v 1 e 1 0 ]
-"47
-[v _eusart1_putch eusart1_putch `(v 1 e 1 0 ]
-"53
-[v _eusart2_putch eusart2_putch `(v 1 e 1 0 ]
-"59
-[v _eusart1_getch eusart1_getch `(uc 1 e 1 0 ]
-"50 C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h
-[v _ANSELA ANSELA `VEuc 1 e 1 @3896 ]
-"95
-[v _ANSELB ANSELB `VEuc 1 e 1 @3897 ]
-"145
-[v _ANSELC ANSELC `VEuc 1 e 1 @3898 ]
-"196
-[v _ANSELD ANSELD `VEuc 1 e 1 @3899 ]
-[s S467 . 1 `uc 1 ABDEN 1 0 :1:0
-`uc 1 WUE 1 0 :1:1
-`uc 1 . 1 0 :1:2
-`uc 1 BRG16 1 0 :1:3
-`uc 1 CKTXP 1 0 :1:4
-`uc 1 DTRXP 1 0 :1:5
-`uc 1 RCIDL 1 0 :1:6
-`uc 1 ABDOVF 1 0 :1:7
-]
-"4328
-[s S476 . 1 `uc 1 . 1 0 :4:0
-`uc 1 SCKP 1 0 :1:4
-]
-[s S716 . 1 `uc 1 ABDEN2 1 0 :1:0
-`uc 1 WUE2 1 0 :1:1
-`uc 1 . 1 0 :1:2
-`uc 1 BRG162 1 0 :1:3
-`uc 1 SCKP2 1 0 :1:4
-`uc 1 DTRXP2 1 0 :1:5
-`uc 1 RCIDL2 1 0 :1:6
-`uc 1 ABDOVF2 1 0 :1:7
-]
-[s S725 . 1 `uc 1 . 1 0 :4:0
-`uc 1 TXCKP2 1 0 :1:4
-`uc 1 RXDTP2 1 0 :1:5
-`uc 1 RCMT2 1 0 :1:6
-]
-[u S730 . 1 `S467 1 . 1 0 `S476 1 . 1 0 `S716 1 . 1 0 `S725 1 . 1 0 ]
-[v _BAUDCON2bits BAUDCON2bits `VES730 1 e 1 @3952 ]
-[s S395 . 1 `uc 1 RX9D 1 0 :1:0
-`uc 1 OERR 1 0 :1:1
-`uc 1 FERR 1 0 :1:2
-`uc 1 ADDEN 1 0 :1:3
-`uc 1 CREN 1 0 :1:4
-`uc 1 SREN 1 0 :1:5
-`uc 1 RX9 1 0 :1:6
-`uc 1 SPEN 1 0 :1:7
-]
-"4593
-[s S404 . 1 `uc 1 . 1 0 :3:0
-`uc 1 ADEN 1 0 :1:3
-]
-[s S651 . 1 `uc 1 RX9D2 1 0 :1:0
-`uc 1 OERR2 1 0 :1:1
-`uc 1 FERR2 1 0 :1:2
-`uc 1 ADDEN2 1 0 :1:3
-`uc 1 CREN2 1 0 :1:4
-`uc 1 SREN2 1 0 :1:5
-`uc 1 RX92 1 0 :1:6
-`uc 1 SPEN2 1 0 :1:7
-]
-[s S660 . 1 `uc 1 RCD82 1 0 :1:0
-`uc 1 . 1 0 :5:1
-`uc 1 RC8_92 1 0 :1:6
-]
-[s S664 . 1 `uc 1 . 1 0 :6:0
-`uc 1 RC92 1 0 :1:6
-]
-[u S667 . 1 `S395 1 . 1 0 `S404 1 . 1 0 `S651 1 . 1 0 `S660 1 . 1 0 `S664 1 . 1 0 ]
-[v _RCSTA2bits RCSTA2bits `VES667 1 e 1 @3953 ]
-[s S346 . 1 `uc 1 TX9D 1 0 :1:0
-`uc 1 TRMT 1 0 :1:1
-`uc 1 BRGH 1 0 :1:2
-`uc 1 SENDB 1 0 :1:3
-`uc 1 SYNC 1 0 :1:4
-`uc 1 TXEN 1 0 :1:5
-`uc 1 TX9 1 0 :1:6
-`uc 1 CSRC 1 0 :1:7
-]
-"4873
-[s S599 . 1 `uc 1 TX9D2 1 0 :1:0
-`uc 1 TRMT2 1 0 :1:1
-`uc 1 BRGH2 1 0 :1:2
-`uc 1 SENDB2 1 0 :1:3
-`uc 1 SYNC2 1 0 :1:4
-`uc 1 TXEN2 1 0 :1:5
-`uc 1 TX92 1 0 :1:6
-`uc 1 CSRC2 1 0 :1:7
-]
-[s S608 . 1 `uc 1 TXD82 1 0 :1:0
-`uc 1 . 1 0 :5:1
-`uc 1 TX8_92 1 0 :1:6
-]
-[u S612 . 1 `S346 1 . 1 0 `S599 1 . 1 0 `S608 1 . 1 0 ]
-[v _TXSTA2bits TXSTA2bits `VES612 1 e 1 @3954 ]
-"5093
-[v _TX2REG TX2REG `VEuc 1 e 1 @3955 ]
-"5164
-[v _SPBRG2 SPBRG2 `VEuc 1 e 1 @3957 ]
-"5202
-[v _SPBRGH2 SPBRGH2 `VEuc 1 e 1 @3958 ]
-"6278
-[v _PORTA PORTA `VEuc 1 e 1 @3968 ]
-"6563
-[v _PORTB PORTB `VEuc 1 e 1 @3969 ]
-"8058
-[v _TRISA TRISA `VEuc 1 e 1 @3986 ]
-"8280
-[v _TRISB TRISB `VEuc 1 e 1 @3987 ]
-[s S550 . 1 `uc 1 TRISC0 1 0 :1:0
-`uc 1 TRISC1 1 0 :1:1
-`uc 1 TRISC2 1 0 :1:2
-`uc 1 TRISC3 1 0 :1:3
-`uc 1 TRISC4 1 0 :1:4
-`uc 1 TRISC5 1 0 :1:5
-`uc 1 TRISC6 1 0 :1:6
-`uc 1 TRISC7 1 0 :1:7
-]
-"8534
-[s S559 . 1 `uc 1 RC0 1 0 :1:0
-`uc 1 RC1 1 0 :1:1
-`uc 1 RC2 1 0 :1:2
-`uc 1 RC3 1 0 :1:3
-`uc 1 RC4 1 0 :1:4
-`uc 1 RC5 1 0 :1:5
-`uc 1 RC6 1 0 :1:6
-`uc 1 RC7 1 0 :1:7
-]
-[u S568 . 1 `S550 1 . 1 0 `S559 1 . 1 0 ]
-[v _TRISCbits TRISCbits `VES568 1 e 1 @3988 ]
-[s S762 . 1 `uc 1 TRISD0 1 0 :1:0
-`uc 1 TRISD1 1 0 :1:1
-`uc 1 TRISD2 1 0 :1:2
-`uc 1 TRISD3 1 0 :1:3
-`uc 1 TRISD4 1 0 :1:4
-`uc 1 TRISD5 1 0 :1:5
-`uc 1 TRISD6 1 0 :1:6
-`uc 1 TRISD7 1 0 :1:7
-]
-"8756
-[s S771 . 1 `uc 1 RD0 1 0 :1:0
-`uc 1 RD1 1 0 :1:1
-`uc 1 RD2 1 0 :1:2
-`uc 1 RD3 1 0 :1:3
-`uc 1 RD4 1 0 :1:4
-`uc 1 RD5 1 0 :1:5
-`uc 1 RD6 1 0 :1:6
-`uc 1 RD7 1 0 :1:7
-]
-[u S780 . 1 `S762 1 . 1 0 `S771 1 . 1 0 ]
-[v _TRISDbits TRISDbits `VES780 1 e 1 @3989 ]
-[s S102 . 1 `uc 1 TUN 1 0 :6:0
-`uc 1 PLLEN 1 0 :1:6
-`uc 1 INTSRC 1 0 :1:7
-]
-"9082
-[s S106 . 1 `uc 1 TUN0 1 0 :1:0
-`uc 1 TUN1 1 0 :1:1
-`uc 1 TUN2 1 0 :1:2
-`uc 1 TUN3 1 0 :1:3
-`uc 1 TUN4 1 0 :1:4
-`uc 1 TUN5 1 0 :1:5
-]
-[u S113 . 1 `S102 1 . 1 0 `S106 1 . 1 0 ]
-[v _OSCTUNEbits OSCTUNEbits `VES113 1 e 1 @3995 ]
-[s S195 . 1 `uc 1 TMR1IE 1 0 :1:0
-`uc 1 TMR2IE 1 0 :1:1
-`uc 1 CCP1IE 1 0 :1:2
-`uc 1 SSP1IE 1 0 :1:3
-`uc 1 TX1IE 1 0 :1:4
-`uc 1 RC1IE 1 0 :1:5
-`uc 1 ADIE 1 0 :1:6
-]
-"9434
-[s S203 . 1 `uc 1 . 1 0 :3:0
-`uc 1 SSPIE 1 0 :1:3
-`uc 1 TXIE 1 0 :1:4
-`uc 1 RCIE 1 0 :1:5
-]
-[u S208 . 1 `S195 1 . 1 0 `S203 1 . 1 0 ]
-[v _PIE1bits PIE1bits `VES208 1 e 1 @3997 ]
-[s S21 . 1 `uc 1 TMR1IF 1 0 :1:0
-`uc 1 TMR2IF 1 0 :1:1
-`uc 1 CCP1IF 1 0 :1:2
-`uc 1 SSP1IF 1 0 :1:3
-`uc 1 TX1IF 1 0 :1:4
-`uc 1 RC1IF 1 0 :1:5
-`uc 1 ADIF 1 0 :1:6
-]
-"9511
-[s S29 . 1 `uc 1 . 1 0 :3:0
-`uc 1 SSPIF 1 0 :1:3
-`uc 1 TXIF 1 0 :1:4
-`uc 1 RCIF 1 0 :1:5
-]
-[u S34 . 1 `S21 1 . 1 0 `S29 1 . 1 0 ]
-[v _PIR1bits PIR1bits `VES34 1 e 1 @3998 ]
-"10396
-[s S407 . 1 `uc 1 RX9D1 1 0 :1:0
-`uc 1 OERR1 1 0 :1:1
-`uc 1 FERR1 1 0 :1:2
-`uc 1 ADDEN1 1 0 :1:3
-`uc 1 CREN1 1 0 :1:4
-`uc 1 SREN1 1 0 :1:5
-`uc 1 RX91 1 0 :1:6
-`uc 1 SPEN1 1 0 :1:7
-]
-[s S416 . 1 `uc 1 RCD8 1 0 :1:0
-`uc 1 . 1 0 :5:1
-`uc 1 RC8_9 1 0 :1:6
-]
-[s S420 . 1 `uc 1 . 1 0 :6:0
-`uc 1 RC9 1 0 :1:6
-]
-[s S423 . 1 `uc 1 . 1 0 :5:0
-`uc 1 SRENA 1 0 :1:5
-]
-[u S426 . 1 `S395 1 . 1 0 `S404 1 . 1 0 `S407 1 . 1 0 `S416 1 . 1 0 `S420 1 . 1 0 `S423 1 . 1 0 ]
-[v _RCSTA1bits RCSTA1bits `VES426 1 e 1 @4011 ]
-"10840
-[s S355 . 1 `uc 1 TX9D1 1 0 :1:0
-`uc 1 TRMT1 1 0 :1:1
-`uc 1 BRGH1 1 0 :1:2
-`uc 1 SENDB1 1 0 :1:3
-`uc 1 SYNC1 1 0 :1:4
-`uc 1 TXEN1 1 0 :1:5
-`uc 1 TX91 1 0 :1:6
-`uc 1 CSRC1 1 0 :1:7
-]
-[s S364 . 1 `uc 1 TXD8 1 0 :1:0
-`uc 1 . 1 0 :5:1
-`uc 1 TX8_9 1 0 :1:6
-]
-[u S368 . 1 `S346 1 . 1 0 `S355 1 . 1 0 `S364 1 . 1 0 ]
-[v _TXSTA1bits TXSTA1bits `VES368 1 e 1 @4012 ]
-"11183
-[v _TX1REG TX1REG `VEuc 1 e 1 @4013 ]
-"11261
-[v _RC1REG RC1REG `VEuc 1 e 1 @4014 ]
-"11330
-[v _SPBRG1 SPBRG1 `VEuc 1 e 1 @4015 ]
-"11408
-[v _SPBRGH1 SPBRGH1 `VEuc 1 e 1 @4016 ]
-"12436
-[s S479 . 1 `uc 1 ABDEN1 1 0 :1:0
-`uc 1 WUE1 1 0 :1:1
-`uc 1 . 1 0 :1:2
-`uc 1 BRG161 1 0 :1:3
-`uc 1 SCKP1 1 0 :1:4
-`uc 1 DTRXP1 1 0 :1:5
-`uc 1 RCIDL1 1 0 :1:6
-`uc 1 ABDOVF1 1 0 :1:7
-]
-[s S488 . 1 `uc 1 . 1 0 :4:0
-`uc 1 TXCKP 1 0 :1:4
-`uc 1 RXDTP 1 0 :1:5
-`uc 1 RCMT 1 0 :1:6
-]
-[s S493 . 1 `uc 1 . 1 0 :4:0
-`uc 1 TXCKP1 1 0 :1:4
-`uc 1 RXDTP1 1 0 :1:5
-`uc 1 RCMT1 1 0 :1:6
-]
-[s S498 . 1 `uc 1 . 1 0 :5:0
-`uc 1 RXCKP 1 0 :1:5
-]
-[s S501 . 1 `uc 1 . 1 0 :1:0
-`uc 1 W4E 1 0 :1:1
-]
-[u S504 . 1 `S467 1 . 1 0 `S476 1 . 1 0 `S479 1 . 1 0 `S488 1 . 1 0 `S493 1 . 1 0 `S498 1 . 1 0 `S501 1 . 1 0 ]
-[v _BAUDCON1bits BAUDCON1bits `VES504 1 e 1 @4024 ]
-[s S167 . 1 `uc 1 T2CKPS 1 0 :2:0
-`uc 1 TMR2ON 1 0 :1:2
-`uc 1 T2OUTPS 1 0 :4:3
-]
-"13217
-[s S171 . 1 `uc 1 T2CKPS0 1 0 :1:0
-`uc 1 T2CKPS1 1 0 :1:1
-`uc 1 . 1 0 :1:2
-`uc 1 T2OUTPS0 1 0 :1:3
-`uc 1 T2OUTPS1 1 0 :1:4
-`uc 1 T2OUTPS2 1 0 :1:5
-`uc 1 T2OUTPS3 1 0 :1:6
-]
-[u S179 . 1 `S167 1 . 1 0 `S171 1 . 1 0 ]
-[v _T2CONbits T2CONbits `VES179 1 e 1 @4026 ]
-"13267
-[v _PR2 PR2 `VEuc 1 e 1 @4027 ]
-[s S128 . 1 `uc 1 SCS 1 0 :2:0
-`uc 1 HFIOFS 1 0 :1:2
-`uc 1 OSTS 1 0 :1:3
-`uc 1 IRCF 1 0 :3:4
-`uc 1 IDLEN 1 0 :1:7
-]
-"16033
-[s S134 . 1 `uc 1 SCS0 1 0 :1:0
-`uc 1 SCS1 1 0 :1:1
-`uc 1 IOFS 1 0 :1:2
-`uc 1 . 1 0 :1:3
-`uc 1 IRCF0 1 0 :1:4
-`uc 1 IRCF1 1 0 :1:5
-`uc 1 IRCF2 1 0 :1:6
-]
-[u S142 . 1 `S128 1 . 1 0 `S134 1 . 1 0 ]
-[v _OSCCONbits OSCCONbits `VES142 1 e 1 @4051 ]
-[s S53 . 1 `uc 1 RBIF 1 0 :1:0
-`uc 1 INT0IF 1 0 :1:1
-`uc 1 TMR0IF 1 0 :1:2
-`uc 1 RBIE 1 0 :1:3
-`uc 1 INT0IE 1 0 :1:4
-`uc 1 TMR0IE 1 0 :1:5
-`uc 1 PEIE_GIEL 1 0 :1:6
-`uc 1 GIE_GIEH 1 0 :1:7
-]
-"16922
-[s S62 . 1 `uc 1 . 1 0 :1:0
-`uc 1 INT0F 1 0 :1:1
-`uc 1 T0IF 1 0 :1:2
-`uc 1 . 1 0 :1:3
-`uc 1 INT0E 1 0 :1:4
-`uc 1 T0IE 1 0 :1:5
-`uc 1 PEIE 1 0 :1:6
-`uc 1 GIE 1 0 :1:7
-]
-[s S71 . 1 `uc 1 . 1 0 :6:0
-`uc 1 GIEL 1 0 :1:6
-`uc 1 GIEH 1 0 :1:7
-]
-[u S75 . 1 `S53 1 . 1 0 `S62 1 . 1 0 `S71 1 . 1 0 ]
-[v _INTCONbits INTCONbits `VES75 1 e 1 @4082 ]
-"18736
-[v _RC1IF RC1IF `VEb 1 e 0 @31989 ]
-"19488
-[v _TX1IF TX1IF `VEb 1 e 0 @31988 ]
-"19496
-[v _TX2IF TX2IF `VEb 1 e 0 @32036 ]
-"106 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _keys_data keys_data `VE[16]ul 1 e 64 0 ]
-"108
-[v _keypresses keypresses `VEui 1 e 2 0 ]
-"220
-[v _main main `(v 1 e 1 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0
-`uc 1 channel 1 0 :4:4
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-"223
-[v main@message message `S233 1 a 7 7 ]
-"222
-[v main@i i `ui 1 a 2 5 ]
-"263
-} 0
-"62 Z:\SAMB_4\projects\xilofono\src\midi.c
-[v _midi_note_on midi_note_on `(i 1 e 2 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0
-`uc 1 channel 1 0 :4:4
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_note_on@pkt pkt `*.39S233 1 p 2 46 ]
-[v midi_note_on@channel channel `ui 1 p 2 48 ]
-[v midi_note_on@note note `E31 1 p 1 50 ]
-[v midi_note_on@velocity velocity `uc 1 p 1 51 ]
-"85
-} 0
-"40
-[v _midi_set_status midi_set_status `(i 1 e 2 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0
-`uc 1 channel 1 0 :4:4
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_set_status@pkt pkt `*.39S233 1 p 2 41 ]
-[v midi_set_status@status status `E40 1 p 1 43 ]
-"49
-} 0
-"51
-[v _midi_set_channel midi_set_channel `(i 1 e 2 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0
-`uc 1 channel 1 0 :4:4
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_set_channel@pkt pkt `*.39S233 1 p 2 41 ]
-[v midi_set_channel@channel channel `ui 1 p 2 43 ]
-"60
-} 0
-"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c
-[v _memset memset `(*.39v 1 e 2 0 ]
-{
-"15
-[v memset@p p `*.39uc 1 a 2 47 ]
-"8
-[v memset@p1 p1 `*.39v 1 p 2 41 ]
-[v memset@c c `i 1 p 2 43 ]
-[v memset@n n `ui 1 p 2 45 ]
-"22
-} 0
-"155 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _init_hw init_hw `T(v 1 e 1 0 ]
-{
-"216
-} 0
-"25 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _eusart2_init eusart2_init `(v 1 e 1 0 ]
-{
-"45
-} 0
-"4
-[v _eusart1_init eusart1_init `(v 1 e 1 0 ]
-{
-"23
-} 0
-"266 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _eusart_write_midi eusart_write_midi `(i 1 e 2 0 ]
-{
-"269
-[v eusart_write_midi@data data `*.39uc 1 a 2 48 ]
-"268
-[v eusart_write_midi@length length `ui 1 a 2 46 ]
-[s S233 . 7 `uc 1 status 1 0 :4:0
-`uc 1 channel 1 0 :4:4
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-"266
-[v eusart_write_midi@pkt pkt `*.39CS233 1 p 2 42 ]
-"285
-} 0
-"53 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _eusart2_putch eusart2_putch `(v 1 e 1 0 ]
-{
-[v eusart2_putch@c c `uc 1 a 1 wreg ]
-[v eusart2_putch@c c `uc 1 a 1 wreg ]
-[v eusart2_putch@c c `uc 1 a 1 41 ]
-"57
-} 0
-"114 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _isr isr `II(v 1 e 1 0 ]
-{
-"116
-[v isr@i i `uc 1 a 1 40 ]
-[v isr@data_b data_b `uc 1 a 1 37 ]
-[v isr@data_a data_a `uc 1 a 1 36 ]
-"152
-} 0
generated by cgit v1.2.1 (git 2.18.0) at 2024-04-27 14:58:36 +0200