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Diffstat (limited to 'src/dist/default/production/src.production.sdb')
| -rw-r--r-- | src/dist/default/production/src.production.sdb | 156 |
1 files changed, 156 insertions, 0 deletions
diff --git a/src/dist/default/production/src.production.sdb b/src/dist/default/production/src.production.sdb new file mode 100644 index 0000000..42af7a3 --- /dev/null +++ b/src/dist/default/production/src.production.sdb @@ -0,0 +1,156 @@ +[p LITE_MODE AUTOSTATIC LFSROK EMI_WORD ] +[d version 1.1 ] +[d edition pro ] +[d chip 18F44K22 ] +[d frameptr 4065 ] +"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\float.c +[v ___ftpack __ftpack `(f 1 e 3 0 ] +"86 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftadd.c +[v ___ftadd __ftadd `(f 1 e 3 0 ] +"54 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftdiv.c +[v ___ftdiv __ftdiv `(f 1 e 3 0 ] +"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftmul.c +[v ___ftmul __ftmul `(f 1 e 3 0 ] +"20 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftsub.c +[v ___ftsub __ftsub `(f 1 e 3 0 ] +"10 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcadd.c +[v ___fladd __fladd `(d 1 e 3 0 ] +"245 +[v ___flsub __flsub `(d 1 e 3 0 ] +"11 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcdiv.c +[v ___fldiv __fldiv `(d 1 e 3 0 ] +"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcmul.c +[v ___flmul __flmul `(d 1 e 3 0 ] +"15 C:\Program Files\Microchip\xc8\v1.44\sources\common\Umul32.c +[v ___lmul __lmul `(ul 1 e 4 0 ] +"83 Z:\SAMB_4\projects\xilofono\src\main.c +[v _main main `(v 1 e 1 0 ] +"4 Z:\SAMB_4\projects\xilofono\src\rs232.c +[v _eusart_init eusart_init `(v 1 e 1 0 ] +"23 +[v _putch putch `(v 1 e 1 0 ] +"29 +[v _getch getch `(uc 1 e 1 0 ] +[s S79 . 1 `uc 1 RX9D 1 0 :1:0 +`uc 1 OERR 1 0 :1:1 +`uc 1 FERR 1 0 :1:2 +`uc 1 ADDEN 1 0 :1:3 +`uc 1 CREN 1 0 :1:4 +`uc 1 SREN 1 0 :1:5 +`uc 1 RX9 1 0 :1:6 +`uc 1 SPEN 1 0 :1:7 +] +"10543 C:\Program Files\Microchip\xc8\v1.44\include\pic18f44k22.h +[s S88 . 1 `uc 1 . 1 0 :3:0 +`uc 1 ADEN 1 0 :1:3 +] +[s S91 . 1 `uc 1 RX9D1 1 0 :1:0 +`uc 1 OERR1 1 0 :1:1 +`uc 1 FERR1 1 0 :1:2 +`uc 1 ADDEN1 1 0 :1:3 +`uc 1 CREN1 1 0 :1:4 +`uc 1 SREN1 1 0 :1:5 +`uc 1 RX91 1 0 :1:6 +`uc 1 SPEN1 1 0 :1:7 +] +[s S100 . 1 `uc 1 RCD8 1 0 :1:0 +`uc 1 . 1 0 :5:1 +`uc 1 RC8_9 1 0 :1:6 +] +[s S104 . 1 `uc 1 . 1 0 :6:0 +`uc 1 RC9 1 0 :1:6 +] +[s S107 . 1 `uc 1 . 1 0 :5:0 +`uc 1 SRENA 1 0 :1:5 +] +[u S110 . 1 `S79 1 . 1 0 `S88 1 . 1 0 `S91 1 . 1 0 `S100 1 . 1 0 `S104 1 . 1 0 `S107 1 . 1 0 ] +[v _RCSTAbits RCSTAbits `VES110 1 e 1 @4011 ] +[s S30 . 1 `uc 1 TX9D 1 0 :1:0 +`uc 1 TRMT 1 0 :1:1 +`uc 1 BRGH 1 0 :1:2 +`uc 1 SENDB 1 0 :1:3 +`uc 1 SYNC 1 0 :1:4 +`uc 1 TXEN 1 0 :1:5 +`uc 1 TX9 1 0 :1:6 +`uc 1 CSRC 1 0 :1:7 +] +"10960 +[s S39 . 1 `uc 1 TX9D1 1 0 :1:0 +`uc 1 TRMT1 1 0 :1:1 +`uc 1 BRGH1 1 0 :1:2 +`uc 1 SENDB1 1 0 :1:3 +`uc 1 SYNC1 1 0 :1:4 +`uc 1 TXEN1 1 0 :1:5 +`uc 1 TX91 1 0 :1:6 +`uc 1 CSRC1 1 0 :1:7 +] +[s S48 . 1 `uc 1 TXD8 1 0 :1:0 +`uc 1 . 1 0 :5:1 +`uc 1 TX8_9 1 0 :1:6 +] +[u S52 . 1 `S30 1 . 1 0 `S39 1 . 1 0 `S48 1 . 1 0 ] +[v _TXSTAbits TXSTAbits `VES52 1 e 1 @4012 ] +"11179 +[v _TXREG TXREG `VEuc 1 e 1 @4013 ] +"11257 +[v _RCREG RCREG `VEuc 1 e 1 @4014 ] +"11335 +[v _SPBRG SPBRG `VEuc 1 e 1 @4015 ] +[s S150 . 1 `uc 1 ABDEN 1 0 :1:0 +`uc 1 WUE 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 BRG16 1 0 :1:3 +`uc 1 CKTXP 1 0 :1:4 +`uc 1 DTRXP 1 0 :1:5 +`uc 1 RCIDL 1 0 :1:6 +`uc 1 ABDOVF 1 0 :1:7 +] +"12600 +[s S159 . 1 `uc 1 . 1 0 :4:0 +`uc 1 SCKP 1 0 :1:4 +] +[s S162 . 1 `uc 1 ABDEN1 1 0 :1:0 +`uc 1 WUE1 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 BRG161 1 0 :1:3 +`uc 1 SCKP1 1 0 :1:4 +`uc 1 DTRXP1 1 0 :1:5 +`uc 1 RCIDL1 1 0 :1:6 +`uc 1 ABDOVF1 1 0 :1:7 +] +[s S171 . 1 `uc 1 . 1 0 :4:0 +`uc 1 TXCKP 1 0 :1:4 +`uc 1 RXDTP 1 0 :1:5 +`uc 1 RCMT 1 0 :1:6 +] +[s S176 . 1 `uc 1 . 1 0 :4:0 +`uc 1 TXCKP1 1 0 :1:4 +`uc 1 RXDTP1 1 0 :1:5 +`uc 1 RCMT1 1 0 :1:6 +] +[s S181 . 1 `uc 1 . 1 0 :5:0 +`uc 1 RXCKP 1 0 :1:5 +] +[s S184 . 1 `uc 1 . 1 0 :1:0 +`uc 1 W4E 1 0 :1:1 +] +[u S187 . 1 `S150 1 . 1 0 `S159 1 . 1 0 `S162 1 . 1 0 `S171 1 . 1 0 `S176 1 . 1 0 `S181 1 . 1 0 `S184 1 . 1 0 ] +[v _BAUDCONbits BAUDCONbits `VES187 1 e 1 @4024 ] +"18768 +[v _RCIF RCIF `VEb 1 e 0 @31989 ] +"19440 +[v _TRISC6 TRISC6 `VEb 1 e 0 @31910 ] +"19442 +[v _TRISC7 TRISC7 `VEb 1 e 0 @31911 ] +"19540 +[v _TXIF TXIF `VEb 1 e 0 @31988 ] +"83 Z:\SAMB_4\projects\xilofono\src\main.c +[v _main main `(v 1 e 1 0 ] +{ +"90 +} 0 +"4 Z:\SAMB_4\projects\xilofono\src\rs232.c +[v _eusart_init eusart_init `(v 1 e 1 0 ] +{ +"21 +} 0 |