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Diffstat (limited to 'src/dist/default/production/src.production.sdb')
-rw-r--r-- | src/dist/default/production/src.production.sdb | 557 |
1 files changed, 557 insertions, 0 deletions
diff --git a/src/dist/default/production/src.production.sdb b/src/dist/default/production/src.production.sdb new file mode 100644 index 0000000..f9bbdf0 --- /dev/null +++ b/src/dist/default/production/src.production.sdb @@ -0,0 +1,557 @@ +[p LITE_MODE AUTOSTATIC LFSROK EMI_WORD ] +[d version 1.1 ] +[d edition pro ] +[d chip 18F45K22 ] +[d frameptr 4065 ] +"216 Z:\SAMB_4\projects\xilofono\src\main.c +[e E41 . `uc +C 0 +D 1 +E 2 +F 3 +G 4 +A 5 +B 6 +] +"41 Z:\SAMB_4\projects\xilofono\src\midi.c +[e E40 . `uc +NOTE_ON 8 +NOTE_OFF 9 +POLYPHONIC_KEYPRESS 10 +CONTROLLER 11 +PROGRAM_CHANGE 12 +CHANNEL_PRESSURE 13 +PITCH_BLEND 15 +] +"63 +[e E31 . `uc +C 0 +D 1 +E 2 +F 3 +G 4 +A 5 +B 6 +] +"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\float.c +[v ___ftpack __ftpack `(f 1 e 3 0 ] +"86 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftadd.c +[v ___ftadd __ftadd `(f 1 e 3 0 ] +"54 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftdiv.c +[v ___ftdiv __ftdiv `(f 1 e 3 0 ] +"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftmul.c +[v ___ftmul __ftmul `(f 1 e 3 0 ] +"20 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftsub.c +[v ___ftsub __ftsub `(f 1 e 3 0 ] +"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c +[v _memset memset `(*.39v 1 e 2 0 ] +"10 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcadd.c +[v ___fladd __fladd `(d 1 e 3 0 ] +"245 +[v ___flsub __flsub `(d 1 e 3 0 ] +"11 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcdiv.c +[v ___fldiv __fldiv `(d 1 e 3 0 ] +"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcmul.c +[v ___flmul __flmul `(d 1 e 3 0 ] +"15 C:\Program Files\Microchip\xc8\v1.44\sources\common\Umul32.c +[v ___lmul __lmul `(ul 1 e 4 0 ] +"101 Z:\SAMB_4\projects\xilofono\src\main.c +[v _isr isr `II(v 1 e 1 0 ] +"140 +[v _init_hw init_hw `T(v 1 e 1 0 ] +"204 +[v _main main `(v 1 e 1 0 ] +"226 +[v _eusart_write_midi eusart_write_midi `(i 1 e 2 0 ] +"40 Z:\SAMB_4\projects\xilofono\src\midi.c +[v _midi_set_status midi_set_status `(i 1 e 2 0 ] +"51 +[v _midi_set_channel midi_set_channel `(i 1 e 2 0 ] +"62 +[v _midi_note_on midi_note_on `(i 1 e 2 0 ] +"4 Z:\SAMB_4\projects\xilofono\src\rs232.c +[v _eusart1_init eusart1_init `(v 1 e 1 0 ] +"29 +[v _putch putch `(v 1 e 1 0 ] +"35 +[v _getch getch `(uc 1 e 1 0 ] +"50 C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h +[v _ANSELA ANSELA `VEuc 1 e 1 @3896 ] +"95 +[v _ANSELB ANSELB `VEuc 1 e 1 @3897 ] +"145 +[v _ANSELC ANSELC `VEuc 1 e 1 @3898 ] +"196 +[v _ANSELD ANSELD `VEuc 1 e 1 @3899 ] +"6278 +[v _PORTA PORTA `VEuc 1 e 1 @3968 ] +[s S160 . 1 `uc 1 RA0 1 0 :1:0 +`uc 1 RA1 1 0 :1:1 +`uc 1 RA2 1 0 :1:2 +`uc 1 RA3 1 0 :1:3 +`uc 1 RA4 1 0 :1:4 +`uc 1 RA5 1 0 :1:5 +`uc 1 RA6 1 0 :1:6 +`uc 1 RA7 1 0 :1:7 +] +"6363 +[s S169 . 1 `uc 1 AN0 1 0 :1:0 +`uc 1 AN1 1 0 :1:1 +`uc 1 AN2 1 0 :1:2 +`uc 1 AN3 1 0 :1:3 +`uc 1 . 1 0 :1:4 +`uc 1 AN4 1 0 :1:5 +] +[s S176 . 1 `uc 1 C12IN0M 1 0 :1:0 +`uc 1 C12IN1M 1 0 :1:1 +`uc 1 C2INP 1 0 :1:2 +`uc 1 C1INP 1 0 :1:3 +`uc 1 C1OUT 1 0 :1:4 +`uc 1 C2OUT 1 0 :1:5 +] +[s S183 . 1 `uc 1 C12IN0N 1 0 :1:0 +`uc 1 C12IN1N 1 0 :1:1 +`uc 1 VREFM 1 0 :1:2 +`uc 1 VREFP 1 0 :1:3 +`uc 1 T0CKI 1 0 :1:4 +`uc 1 SS 1 0 :1:5 +] +[s S190 . 1 `uc 1 . 1 0 :5:0 +`uc 1 NOT_SS 1 0 :1:5 +] +[s S193 . 1 `uc 1 . 1 0 :2:0 +`uc 1 VREFN 1 0 :1:2 +`uc 1 . 1 0 :1:3 +`uc 1 SRQ 1 0 :1:4 +`uc 1 nSS 1 0 :1:5 +] +[s S199 . 1 `uc 1 . 1 0 :2:0 +`uc 1 CVREF 1 0 :1:2 +`uc 1 . 1 0 :2:3 +`uc 1 LVDIN 1 0 :1:5 +] +[s S204 . 1 `uc 1 . 1 0 :2:0 +`uc 1 DACOUT 1 0 :1:2 +`uc 1 . 1 0 :2:3 +`uc 1 HLVDIN 1 0 :1:5 +] +[s S209 . 1 `uc 1 . 1 0 :5:0 +`uc 1 SS1 1 0 :1:5 +] +[s S212 . 1 `uc 1 . 1 0 :5:0 +`uc 1 NOT_SS1 1 0 :1:5 +] +[s S215 . 1 `uc 1 . 1 0 :5:0 +`uc 1 nSS1 1 0 :1:5 +] +[s S218 . 1 `uc 1 . 1 0 :5:0 +`uc 1 SRNQ 1 0 :1:5 +] +[s S221 . 1 `uc 1 ULPWUIN 1 0 :1:0 +`uc 1 . 1 0 :6:1 +`uc 1 RJPU 1 0 :1:7 +] +[u S225 . 1 `S160 1 . 1 0 `S169 1 . 1 0 `S176 1 . 1 0 `S183 1 . 1 0 `S190 1 . 1 0 `S193 1 . 1 0 `S199 1 . 1 0 `S204 1 . 1 0 `S209 1 . 1 0 `S212 1 . 1 0 `S215 1 . 1 0 `S218 1 . 1 0 `S221 1 . 1 0 ] +[v _PORTAbits PORTAbits `VES225 1 e 1 @3968 ] +"6563 +[v _PORTB PORTB `VEuc 1 e 1 @3969 ] +[s S21 . 1 `uc 1 RD0 1 0 :1:0 +`uc 1 RD1 1 0 :1:1 +`uc 1 RD2 1 0 :1:2 +`uc 1 RD3 1 0 :1:3 +`uc 1 RD4 1 0 :1:4 +`uc 1 RD5 1 0 :1:5 +`uc 1 RD6 1 0 :1:6 +`uc 1 RD7 1 0 :1:7 +] +"7203 +[s S30 . 1 `uc 1 . 1 0 :2:0 +`uc 1 P2B 1 0 :1:2 +`uc 1 P2C 1 0 :1:3 +`uc 1 P2D 1 0 :1:4 +`uc 1 P1B 1 0 :1:5 +`uc 1 P1C 1 0 :1:6 +`uc 1 P1D 1 0 :1:7 +] +[s S38 . 1 `uc 1 . 1 0 :1:0 +`uc 1 CCP4 1 0 :1:1 +`uc 1 . 1 0 :4:2 +`uc 1 TX2 1 0 :1:6 +`uc 1 RX2 1 0 :1:7 +] +[s S44 . 1 `uc 1 . 1 0 :3:0 +`uc 1 NOT_SS2 1 0 :1:3 +] +[s S47 . 1 `uc 1 SCK2 1 0 :1:0 +`uc 1 SDI2 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 nSS2 1 0 :1:3 +`uc 1 SDO2 1 0 :1:4 +`uc 1 . 1 0 :1:5 +`uc 1 CK2 1 0 :1:6 +`uc 1 DT2 1 0 :1:7 +] +[s S56 . 1 `uc 1 SCL2 1 0 :1:0 +`uc 1 SDA2 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 SS2 1 0 :1:3 +] +[s S61 . 1 `uc 1 AN20 1 0 :1:0 +`uc 1 AN21 1 0 :1:1 +`uc 1 AN22 1 0 :1:2 +`uc 1 AN23 1 0 :1:3 +`uc 1 AN24 1 0 :1:4 +`uc 1 AN25 1 0 :1:5 +`uc 1 AN26 1 0 :1:6 +`uc 1 AN27 1 0 :1:7 +] +[u S70 . 1 `S21 1 . 1 0 `S30 1 . 1 0 `S38 1 . 1 0 `S44 1 . 1 0 `S47 1 . 1 0 `S56 1 . 1 0 `S61 1 . 1 0 ] +[v _PORTDbits PORTDbits `VES70 1 e 1 @3971 ] +"8058 +[v _TRISA TRISA `VEuc 1 e 1 @3986 ] +"8280 +[v _TRISB TRISB `VEuc 1 e 1 @3987 ] +[s S855 . 1 `uc 1 TRISC0 1 0 :1:0 +`uc 1 TRISC1 1 0 :1:1 +`uc 1 TRISC2 1 0 :1:2 +`uc 1 TRISC3 1 0 :1:3 +`uc 1 TRISC4 1 0 :1:4 +`uc 1 TRISC5 1 0 :1:5 +`uc 1 TRISC6 1 0 :1:6 +`uc 1 TRISC7 1 0 :1:7 +] +"8534 +[s S864 . 1 `uc 1 RC0 1 0 :1:0 +`uc 1 RC1 1 0 :1:1 +`uc 1 RC2 1 0 :1:2 +`uc 1 RC3 1 0 :1:3 +`uc 1 RC4 1 0 :1:4 +`uc 1 RC5 1 0 :1:5 +`uc 1 RC6 1 0 :1:6 +`uc 1 RC7 1 0 :1:7 +] +[u S873 . 1 `S855 1 . 1 0 `S864 1 . 1 0 ] +[v _TRISCbits TRISCbits `VES873 1 e 1 @3988 ] +[s S418 . 1 `uc 1 TRISD0 1 0 :1:0 +`uc 1 TRISD1 1 0 :1:1 +`uc 1 TRISD2 1 0 :1:2 +`uc 1 TRISD3 1 0 :1:3 +`uc 1 TRISD4 1 0 :1:4 +`uc 1 TRISD5 1 0 :1:5 +`uc 1 TRISD6 1 0 :1:6 +`uc 1 TRISD7 1 0 :1:7 +] +"8756 +[u S436 . 1 `S418 1 . 1 0 `S21 1 . 1 0 ] +[v _TRISDbits TRISDbits `VES436 1 e 1 @3989 ] +[s S354 . 1 `uc 1 TUN 1 0 :6:0 +`uc 1 PLLEN 1 0 :1:6 +`uc 1 INTSRC 1 0 :1:7 +] +"9082 +[s S358 . 1 `uc 1 TUN0 1 0 :1:0 +`uc 1 TUN1 1 0 :1:1 +`uc 1 TUN2 1 0 :1:2 +`uc 1 TUN3 1 0 :1:3 +`uc 1 TUN4 1 0 :1:4 +`uc 1 TUN5 1 0 :1:5 +] +[u S365 . 1 `S354 1 . 1 0 `S358 1 . 1 0 ] +[v _OSCTUNEbits OSCTUNEbits `VES365 1 e 1 @3995 ] +[s S487 . 1 `uc 1 TMR1IE 1 0 :1:0 +`uc 1 TMR2IE 1 0 :1:1 +`uc 1 CCP1IE 1 0 :1:2 +`uc 1 SSP1IE 1 0 :1:3 +`uc 1 TX1IE 1 0 :1:4 +`uc 1 RC1IE 1 0 :1:5 +`uc 1 ADIE 1 0 :1:6 +] +"9434 +[s S495 . 1 `uc 1 . 1 0 :3:0 +`uc 1 SSPIE 1 0 :1:3 +`uc 1 TXIE 1 0 :1:4 +`uc 1 RCIE 1 0 :1:5 +] +[u S500 . 1 `S487 1 . 1 0 `S495 1 . 1 0 ] +[v _PIE1bits PIE1bits `VES500 1 e 1 @3997 ] +[s S128 . 1 `uc 1 TMR1IF 1 0 :1:0 +`uc 1 TMR2IF 1 0 :1:1 +`uc 1 CCP1IF 1 0 :1:2 +`uc 1 SSP1IF 1 0 :1:3 +`uc 1 TX1IF 1 0 :1:4 +`uc 1 RC1IF 1 0 :1:5 +`uc 1 ADIF 1 0 :1:6 +] +"9511 +[s S136 . 1 `uc 1 . 1 0 :3:0 +`uc 1 SSPIF 1 0 :1:3 +`uc 1 TXIF 1 0 :1:4 +`uc 1 RCIF 1 0 :1:5 +] +[u S141 . 1 `S128 1 . 1 0 `S136 1 . 1 0 ] +[v _PIR1bits PIR1bits `VES141 1 e 1 @3998 ] +[s S700 . 1 `uc 1 RX9D 1 0 :1:0 +`uc 1 OERR 1 0 :1:1 +`uc 1 FERR 1 0 :1:2 +`uc 1 ADDEN 1 0 :1:3 +`uc 1 CREN 1 0 :1:4 +`uc 1 SREN 1 0 :1:5 +`uc 1 RX9 1 0 :1:6 +`uc 1 SPEN 1 0 :1:7 +] +"10396 +[s S709 . 1 `uc 1 . 1 0 :3:0 +`uc 1 ADEN 1 0 :1:3 +] +[s S712 . 1 `uc 1 RX9D1 1 0 :1:0 +`uc 1 OERR1 1 0 :1:1 +`uc 1 FERR1 1 0 :1:2 +`uc 1 ADDEN1 1 0 :1:3 +`uc 1 CREN1 1 0 :1:4 +`uc 1 SREN1 1 0 :1:5 +`uc 1 RX91 1 0 :1:6 +`uc 1 SPEN1 1 0 :1:7 +] +[s S721 . 1 `uc 1 RCD8 1 0 :1:0 +`uc 1 . 1 0 :5:1 +`uc 1 RC8_9 1 0 :1:6 +] +[s S725 . 1 `uc 1 . 1 0 :6:0 +`uc 1 RC9 1 0 :1:6 +] +[s S728 . 1 `uc 1 . 1 0 :5:0 +`uc 1 SRENA 1 0 :1:5 +] +[u S731 . 1 `S700 1 . 1 0 `S709 1 . 1 0 `S712 1 . 1 0 `S721 1 . 1 0 `S725 1 . 1 0 `S728 1 . 1 0 ] +[v _RCSTA1bits RCSTA1bits `VES731 1 e 1 @4011 ] +[s S651 . 1 `uc 1 TX9D 1 0 :1:0 +`uc 1 TRMT 1 0 :1:1 +`uc 1 BRGH 1 0 :1:2 +`uc 1 SENDB 1 0 :1:3 +`uc 1 SYNC 1 0 :1:4 +`uc 1 TXEN 1 0 :1:5 +`uc 1 TX9 1 0 :1:6 +`uc 1 CSRC 1 0 :1:7 +] +"10840 +[s S660 . 1 `uc 1 TX9D1 1 0 :1:0 +`uc 1 TRMT1 1 0 :1:1 +`uc 1 BRGH1 1 0 :1:2 +`uc 1 SENDB1 1 0 :1:3 +`uc 1 SYNC1 1 0 :1:4 +`uc 1 TXEN1 1 0 :1:5 +`uc 1 TX91 1 0 :1:6 +`uc 1 CSRC1 1 0 :1:7 +] +[s S669 . 1 `uc 1 TXD8 1 0 :1:0 +`uc 1 . 1 0 :5:1 +`uc 1 TX8_9 1 0 :1:6 +] +[u S673 . 1 `S651 1 . 1 0 `S660 1 . 1 0 `S669 1 . 1 0 ] +[v _TXSTA1bits TXSTA1bits `VES673 1 e 1 @4012 ] +"11183 +[v _TX1REG TX1REG `VEuc 1 e 1 @4013 ] +"11261 +[v _RC1REG RC1REG `VEuc 1 e 1 @4014 ] +"11330 +[v _SPBRG1 SPBRG1 `VEuc 1 e 1 @4015 ] +"11408 +[v _SPBRGH1 SPBRGH1 `VEuc 1 e 1 @4016 ] +[s S772 . 1 `uc 1 ABDEN 1 0 :1:0 +`uc 1 WUE 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 BRG16 1 0 :1:3 +`uc 1 CKTXP 1 0 :1:4 +`uc 1 DTRXP 1 0 :1:5 +`uc 1 RCIDL 1 0 :1:6 +`uc 1 ABDOVF 1 0 :1:7 +] +"12436 +[s S781 . 1 `uc 1 . 1 0 :4:0 +`uc 1 SCKP 1 0 :1:4 +] +[s S784 . 1 `uc 1 ABDEN1 1 0 :1:0 +`uc 1 WUE1 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 BRG161 1 0 :1:3 +`uc 1 SCKP1 1 0 :1:4 +`uc 1 DTRXP1 1 0 :1:5 +`uc 1 RCIDL1 1 0 :1:6 +`uc 1 ABDOVF1 1 0 :1:7 +] +[s S793 . 1 `uc 1 . 1 0 :4:0 +`uc 1 TXCKP 1 0 :1:4 +`uc 1 RXDTP 1 0 :1:5 +`uc 1 RCMT 1 0 :1:6 +] +[s S798 . 1 `uc 1 . 1 0 :4:0 +`uc 1 TXCKP1 1 0 :1:4 +`uc 1 RXDTP1 1 0 :1:5 +`uc 1 RCMT1 1 0 :1:6 +] +[s S803 . 1 `uc 1 . 1 0 :5:0 +`uc 1 RXCKP 1 0 :1:5 +] +[s S806 . 1 `uc 1 . 1 0 :1:0 +`uc 1 W4E 1 0 :1:1 +] +[u S809 . 1 `S772 1 . 1 0 `S781 1 . 1 0 `S784 1 . 1 0 `S793 1 . 1 0 `S798 1 . 1 0 `S803 1 . 1 0 `S806 1 . 1 0 ] +[v _BAUDCON1bits BAUDCON1bits `VES809 1 e 1 @4024 ] +[s S459 . 1 `uc 1 T2CKPS 1 0 :2:0 +`uc 1 TMR2ON 1 0 :1:2 +`uc 1 T2OUTPS 1 0 :4:3 +] +"13217 +[s S463 . 1 `uc 1 T2CKPS0 1 0 :1:0 +`uc 1 T2CKPS1 1 0 :1:1 +`uc 1 . 1 0 :1:2 +`uc 1 T2OUTPS0 1 0 :1:3 +`uc 1 T2OUTPS1 1 0 :1:4 +`uc 1 T2OUTPS2 1 0 :1:5 +`uc 1 T2OUTPS3 1 0 :1:6 +] +[u S471 . 1 `S459 1 . 1 0 `S463 1 . 1 0 ] +[v _T2CONbits T2CONbits `VES471 1 e 1 @4026 ] +"13267 +[v _PR2 PR2 `VEuc 1 e 1 @4027 ] +[s S380 . 1 `uc 1 SCS 1 0 :2:0 +`uc 1 HFIOFS 1 0 :1:2 +`uc 1 OSTS 1 0 :1:3 +`uc 1 IRCF 1 0 :3:4 +`uc 1 IDLEN 1 0 :1:7 +] +"16033 +[s S386 . 1 `uc 1 SCS0 1 0 :1:0 +`uc 1 SCS1 1 0 :1:1 +`uc 1 IOFS 1 0 :1:2 +`uc 1 . 1 0 :1:3 +`uc 1 IRCF0 1 0 :1:4 +`uc 1 IRCF1 1 0 :1:5 +`uc 1 IRCF2 1 0 :1:6 +] +[u S394 . 1 `S380 1 . 1 0 `S386 1 . 1 0 ] +[v _OSCCONbits OSCCONbits `VES394 1 e 1 @4051 ] +[s S305 . 1 `uc 1 RBIF 1 0 :1:0 +`uc 1 INT0IF 1 0 :1:1 +`uc 1 TMR0IF 1 0 :1:2 +`uc 1 RBIE 1 0 :1:3 +`uc 1 INT0IE 1 0 :1:4 +`uc 1 TMR0IE 1 0 :1:5 +`uc 1 PEIE_GIEL 1 0 :1:6 +`uc 1 GIE_GIEH 1 0 :1:7 +] +"16922 +[s S314 . 1 `uc 1 . 1 0 :1:0 +`uc 1 INT0F 1 0 :1:1 +`uc 1 T0IF 1 0 :1:2 +`uc 1 . 1 0 :1:3 +`uc 1 INT0E 1 0 :1:4 +`uc 1 T0IE 1 0 :1:5 +`uc 1 PEIE 1 0 :1:6 +`uc 1 GIE 1 0 :1:7 +] +[s S323 . 1 `uc 1 . 1 0 :6:0 +`uc 1 GIEL 1 0 :1:6 +`uc 1 GIEH 1 0 :1:7 +] +[u S327 . 1 `S305 1 . 1 0 `S314 1 . 1 0 `S323 1 . 1 0 ] +[v _INTCONbits INTCONbits `VES327 1 e 1 @4082 ] +"18736 +[v _RC1IF RC1IF `VEb 1 e 0 @31989 ] +"19488 +[v _TX1IF TX1IF `VEb 1 e 0 @31988 ] +"95 Z:\SAMB_4\projects\xilofono\src\main.c +[v _keypresses keypresses `VE[15]ui 1 e 30 0 ] +"204 +[v _main main `(v 1 e 1 0 ] +{ +[s S521 . 7 `uc 1 status 1 0 :4:0 +`uc 1 channel 1 0 :4:4 +`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ] +"207 +[v main@sample_message sample_message `S521 1 a 7 2 ] +"223 +} 0 +"62 Z:\SAMB_4\projects\xilofono\src\midi.c +[v _midi_note_on midi_note_on `(i 1 e 2 0 ] +{ +[s S521 . 7 `uc 1 status 1 0 :4:0 +`uc 1 channel 1 0 :4:4 +`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ] +[v midi_note_on@pkt pkt `*.39S521 1 p 2 30 ] +[v midi_note_on@channel channel `ui 1 p 2 32 ] +[v midi_note_on@note note `E31 1 p 1 34 ] +[v midi_note_on@velocity velocity `uc 1 p 1 35 ] +"83 +} 0 +"40 +[v _midi_set_status midi_set_status `(i 1 e 2 0 ] +{ +[s S521 . 7 `uc 1 status 1 0 :4:0 +`uc 1 channel 1 0 :4:4 +`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ] +[v midi_set_status@pkt pkt `*.39S521 1 p 2 25 ] +[v midi_set_status@status status `E40 1 p 1 27 ] +"49 +} 0 +"51 +[v _midi_set_channel midi_set_channel `(i 1 e 2 0 ] +{ +[s S521 . 7 `uc 1 status 1 0 :4:0 +`uc 1 channel 1 0 :4:4 +`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ] +[v midi_set_channel@pkt pkt `*.39S521 1 p 2 25 ] +[v midi_set_channel@channel channel `ui 1 p 2 27 ] +"60 +} 0 +"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c +[v _memset memset `(*.39v 1 e 2 0 ] +{ +"15 +[v memset@p p `*.39uc 1 a 2 31 ] +"8 +[v memset@p1 p1 `*.39v 1 p 2 25 ] +[v memset@c c `i 1 p 2 27 ] +[v memset@n n `ui 1 p 2 29 ] +"22 +} 0 +"140 Z:\SAMB_4\projects\xilofono\src\main.c +[v _init_hw init_hw `T(v 1 e 1 0 ] +{ +"200 +} 0 +"4 Z:\SAMB_4\projects\xilofono\src\rs232.c +[v _eusart1_init eusart1_init `(v 1 e 1 0 ] +{ +"22 +} 0 +"226 Z:\SAMB_4\projects\xilofono\src\main.c +[v _eusart_write_midi eusart_write_midi `(i 1 e 2 0 ] +{ +"229 +[v eusart_write_midi@data data `*.39uc 1 a 2 32 ] +"228 +[v eusart_write_midi@length length `ui 1 a 2 30 ] +[s S521 . 7 `uc 1 status 1 0 :4:0 +`uc 1 channel 1 0 :4:4 +`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ] +"226 +[v eusart_write_midi@pkt pkt `*.39CS521 1 p 2 26 ] +"245 +} 0 +"29 Z:\SAMB_4\projects\xilofono\src\rs232.c +[v _putch putch `(v 1 e 1 0 ] +{ +[v putch@c c `uc 1 a 1 wreg ] +[v putch@c c `uc 1 a 1 wreg ] +[v putch@c c `uc 1 a 1 25 ] +"33 +} 0 +"101 Z:\SAMB_4\projects\xilofono\src\main.c +[v _isr isr `II(v 1 e 1 0 ] +{ +"103 +[v isr@i i `uc 1 a 1 24 ] +[v isr@data data `uc 1 a 1 23 ] +"137 +} 0 |