path: root/src/disassembly/listing.disasm

Disassembly Listing for Xilofono
Generated From:
Z:/SAMB_4/projects/xilofono/src/dist/default/production/src.production.elf
27-feb-2018 09:19:21

---  Z:/SAMB_4/projects/xilofono/src/rs232.c  -----------------------------------------------------------
1:             #include "rs232.h"
2:             #include <xc.h>
3:             
4:             void eusart1_init(void)
5:             {
6:                 // set Async and 8 bits frame
7:                 TXSTA1bits.SYNC = 0;
0598  98AC     BCF TXSTA1, 4, ACCESS
8:                 TXSTA1bits.TX9 = 0;
059A  9CAC     BCF TXSTA1, 6, ACCESS
9:                 
10:                // baud prescaler
11:                RCSTA1bits.SPEN = 1;
059C  8EAB     BSF RCSTA1, 7, ACCESS
12:                SPBRG1 = 31;
059E  0E1F     MOVLW 0x1F
05A0  6EAF     MOVWF SPBRG1, ACCESS
13:                SPBRGH1 = 0;
05A2  0E00     MOVLW 0x0
05A4  6EB0     MOVWF SPBRGH1, ACCESS
14:                TXSTA1bits.BRGH = 0;
05A6  94AC     BCF TXSTA1, 2, ACCESS
15:                BAUDCON1bits.BRG16 = 0;
05A8  96B8     BCF BAUDCON1, 3, ACCESS
16:                
17:                // set up TX / RX pins
18:                TRISCbits.TRISC7 = 1;
05AA  8E94     BSF TRISC, 7, ACCESS
19:                TRISCbits.TRISC6 = 1;
05AC  8C94     BSF TRISC, 6, ACCESS
20:                RCSTA1bits.CREN = 1; // enable continuous reception
05AE  88AB     BSF RCSTA1, 4, ACCESS
21:                TXSTA1bits.TXEN = 1;
05B0  8AAC     BSF TXSTA1, 5, ACCESS
22:            }
05B2  0012     RETURN 0
23:            
24:            void eusart2_init(void)
25:            {
26:                // TODO
27:            }
28:            
29:            void putch(char c)
05B4  0100     MOVLB 0x0
05B6  6F60     MOVWF __pcstackBANK0, BANKED
30:            {
31:                while (!TX1IF);
05B8  A89E     BTFSS PIR1, 4, ACCESS
05BA  D7FE     BRA 0x5B8
32:                TX1REG = c;
05BC  C060     MOVFF __pcstackBANK0, TXREG1
05BE  FFAD     NOP
33:            }
0008  8245     BSF btemp, 1, ACCESS
000A  CFFA     MOVFF PCLATH, 0x2B
000C  F02B     NOP
000E  CFFB     MOVFF PCLATU, 0x2C
0010  F02C     NOP
0012  CFE9     MOVFF FSR0, 0x2D
0014  F02D     NOP
0016  CFEA     MOVFF FSR0H, 0x2E
0018  F02E     NOP
001A  CFE1     MOVFF FSR1, 0x2F
001C  F02F     NOP
001E  CFE2     MOVFF FSR1H, 0x30
0020  F030     NOP
0022  CFD9     MOVFF FSR2, 0x31
0024  F031     NOP
0026  CFDA     MOVFF FSR2H, 0x32
0028  F032     NOP
002A  CFF3     MOVFF PROD, 0x33
002C  F033     NOP
002E  CFF4     MOVFF PRODH, 0x34
0030  F034     NOP
0032  CFF6     MOVFF TBLPTR, 0x35
0034  F035     NOP
0036  CFF7     MOVFF TBLPTRH, 0x36
0038  F036     NOP
003A  CFF8     MOVFF TBLPTRU, 0x37
003C  F037     NOP
003E  CFF5     MOVFF TABLAT, 0x38
0040  F038     NOP
0042  C045     MOVFF btemp, 0x39
0044  F039     NOP
0046  C046     MOVFF 0x46, 0x3A
0048  F03A     NOP
004A  C047     MOVFF 0x47, 0x3B
004C  F03B     NOP
004E  C048     MOVFF 0x48, 0x3C
0050  F03C     NOP
05C0  0012     RETURN 0
34:            
35:            char getch(void)
36:            {
37:                while (!RC1IF);
38:                return RC1REG;
39:            }
40:            
41:            char getche(void)
42:            {
43:                char c = getch();
44:                putch(c); // echo
45:                
46:                return c;
47:            }
---  Z:/SAMB_4/projects/xilofono/src/midi.c  ------------------------------------------------------------
1:             #include "midi.h"
2:             
3:             #include <stdint.h>
4:             #include <stddef.h>
5:             #include <stdio.h>
6:             #include <stdlib.h>
7:             
8:             
9:             #ifdef MIDI_DYNAMIC_MEMORY_ALLOC
10:            midi_message_t *midi_alloc_message(size_t data_size)
11:            {
12:                return (midi_message_t *) malloc(sizeof(midi_message_t) + data_size);
13:            }
14:            
15:            void midi_free_message(midi_message_t *pkt)
16:            {
17:                if (pkt == NULL) {
18:                    return;
19:                }
20:                
21:                free(pkt);
22:                pkt = NULL;
23:            }
24:            
25:            size_t midi_message_size(const midi_message_t *pkt)
26:            {
27:                if (pkt == NULL) {
28:                    return 0;   
29:                }
30:                
31:                switch (pkt->status) {
32:                    case NOTE_ON:  return sizeof(midi_message_t) + 2;
33:                    case NOTE_OFF: return sizeof(midi_message_t) + 1;
34:                    default:       return sizeof(midi_message_t);
35:                }
36:            }
37:            #endif
38:            
39:            
40:            int midi_set_status(midi_message_t *pkt, midi_status_t status)
41:            {
42:                if (pkt == NULL) {
0572  0100     MOVLB 0x0
0574  5160     MOVF __pcstackBANK0, W, BANKED
0576  1161     IORWF pkt, W, BANKED
0578  B4D8     BTFSC STATUS, 2, ACCESS
057A  0012     RETURN 0
43:                    return -1;
44:                }
45:                
46:                pkt->status = status & 0x0F;
057C  C062     MOVFF c, 0x63
057E  F063     NOP
0580  0E0F     MOVLW 0xF
0582  1763     ANDWF 0x63, F, BANKED
0584  C060     MOVFF __pcstackBANK0, FSR2
0586  FFD9     NOP
0588  C061     MOVFF pkt, FSR2H
058A  FFDA     NOP
058C  50DF     MOVF INDF2, W, ACCESS
058E  1963     XORWF 0x63, W, BANKED
0590  0BF0     ANDLW 0xF0
0592  1963     XORWF 0x63, W, BANKED
0594  6EDF     MOVWF INDF2, ACCESS
0596  0012     RETURN 0
47:                
48:                return 0;
49:            }
50:            
51:            int midi_set_channel(midi_message_t *pkt, unsigned channel)
52:            {
53:                if (pkt == NULL) {
054A  0100     MOVLB 0x0
054C  5160     MOVF __pcstackBANK0, W, BANKED
054E  1161     IORWF pkt, W, BANKED
0550  B4D8     BTFSC STATUS, 2, ACCESS
0552  0012     RETURN 0
54:                    return -1;
55:                }
56:                
57:                pkt->channel = channel & 0x0F;
0554  C062     MOVFF c, n
0556  F064     NOP
0558  0E0F     MOVLW 0xF
055A  1764     ANDWF n, F, BANKED
055C  C060     MOVFF __pcstackBANK0, FSR2
055E  FFD9     NOP
0560  C061     MOVFF pkt, FSR2H
0562  FFDA     NOP
0564  3B64     SWAPF n, F, BANKED
0566  50DF     MOVF INDF2, W, ACCESS
0568  1964     XORWF n, W, BANKED
056A  0B0F     ANDLW 0xF
056C  1964     XORWF n, W, BANKED
056E  6EDF     MOVWF INDF2, ACCESS
0570  0012     RETURN 0
58:                
59:                return 0;
60:            }
61:            
62:            int midi_note_on(midi_message_t *pkt, unsigned channel, midi_note_t note, uint8_t velocity)
63:            {
64:                if (pkt == NULL) {
0424  0100     MOVLB 0x0
0426  5165     MOVF pkt, W, BANKED
0428  1166     IORWF p, W, BANKED
042A  B4D8     BTFSC STATUS, 2, ACCESS
042C  0012     RETURN 0
65:                    return -1;
66:                }
67:            
68:            #ifdef MIDI_DYNAMIC_MEMORY_ALLOC
69:                if (pkt->data == NULL) {
70:                    return -2;
71:                }
72:            #endif
73:                
74:                midi_set_status(pkt, NOTE_ON);
042E  C065     MOVFF pkt, __pcstackBANK0
0430  F060     NOP
0432  C066     MOVFF p, pkt
0434  F061     NOP
0436  0E08     MOVLW 0x8
0438  6F62     MOVWF c, BANKED
043A  ECB9     CALL 0x572, 0
043C  F002     NOP
75:                midi_set_channel(pkt, channel);
043E  C065     MOVFF pkt, __pcstackBANK0
0440  F060     NOP
0442  C066     MOVFF p, pkt
0444  F061     NOP
0446  C067     MOVFF channel, c
0448  F062     NOP
044A  C068     MOVFF 0x68, 0x63
044C  F063     NOP
044E  ECA5     CALL 0x54A, 0
0450  F002     NOP
76:                
77:                pkt->data[0] = note;
0452  0100     MOVLB 0x0
0454  EE20     LFSR 2, 0x3
0456  F003     NOP
0458  5165     MOVF pkt, W, BANKED
045A  26D9     ADDWF FSR2, F, ACCESS
045C  5166     MOVF p, W, BANKED
045E  22DA     ADDWFC FSR2H, F, ACCESS
0460  C069     MOVFF note, INDF2
0462  FFDF     NOP
78:                pkt->data[1] = velocity;
0464  EE20     LFSR 2, 0x4
0466  F004     NOP
0468  5165     MOVF pkt, W, BANKED
046A  26D9     ADDWF FSR2, F, ACCESS
046C  5166     MOVF p, W, BANKED
046E  22DA     ADDWFC FSR2H, F, ACCESS
0470  C06A     MOVFF velocity, INDF2
0472  FFDF     NOP
79:                
80:            #ifndef MIDI_DYNAMIC_MEMORY_ALLOC
81:                pkt->data_size = 2;
0474  EE20     LFSR 2, 0x1
0476  F001     NOP
0478  5165     MOVF pkt, W, BANKED
047A  26D9     ADDWF FSR2, F, ACCESS
047C  5166     MOVF p, W, BANKED
047E  22DA     ADDWFC FSR2H, F, ACCESS
0480  0E02     MOVLW 0x2
0482  6EDE     MOVWF POSTINC2, ACCESS
0484  0E00     MOVLW 0x0
0486  6EDD     MOVWF POSTDEC2, ACCESS
0488  0012     RETURN 0
82:            #endif
83:                
84:                return 0;
85:            }
86:            
87:            int midi_note_off(midi_message_t *pkt, unsigned channel, midi_note_t note, uint8_t velocity)
88:            {
89:                if (pkt == NULL) {
90:                    return -1;
91:                }
92:            
93:            #ifdef MIDI_DYNAMIC_MEMORY_ALLOC
94:                if (pkt->data == NULL) {
95:                    return -2;
96:                }
97:            #endif
98:                
99:                midi_set_status(pkt, NOTE_OFF);
100:               midi_set_channel(pkt, channel);
101:               
102:               pkt->data[0] = note;
103:               pkt->data[1] = velocity;
104:               
105:           #ifndef MIDI_DYNAMIC_MEMORY_ALLOC
106:               pkt->data_size = 2;
107:           #endif
108:               
109:               return 0;
110:           }
---  Z:/SAMB_4/projects/xilofono/src/main.c  ------------------------------------------------------------
1:             /*
2:              * File:    main.c
3:              * Author:  Naoki Pross 4E
4:              * Date:    08.01.2018
5:              * Target:  PIC18F44K22
6:              * Version  1.0
7:              * 
8:              * Description:
9:              * 
10:             * Main program for the Xylophone project.
11:             */
12:            
13:            // PIC18F44K22 Configuration Bit Settings
14:            // 'C' source line config statements
15:            
16:            // CONFIG1H
17:            #pragma config FOSC = INTIO7    // Oscillator Selection bits (Internal oscillator block)
18:            #pragma config PLLCFG = ON      // 4X PLL Enable (Oscillator multiplied by 4)
19:            #pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock is always enabled)
20:            #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
21:            #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
22:            
23:            // CONFIG2L
24:            #pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer disabled)
25:            #pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
26:            #pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
27:            
28:            // CONFIG2H
29:            #pragma config WDTEN = ON       // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
30:            #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
31:            
32:            // CONFIG3H
33:            #pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
34:            #pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
35:            #pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
36:            #pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
37:            #pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
38:            #pragma config P2BMX = PORTD2   // ECCP2 B output mux bit (P2B is on RD2)
39:            #pragma config MCLRE = EXTMCLR  // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
40:            
41:            // CONFIG4L
42:            #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
43:            #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
44:            #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
45:            
46:            // CONFIG5L
47:            #pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
48:            #pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
49:            #pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
50:            #pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
51:            
52:            // CONFIG5H
53:            #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
54:            #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
55:            
56:            // CONFIG6L
57:            #pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
58:            #pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
59:            #pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
60:            #pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
61:            
62:            // CONFIG6H
63:            #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
64:            #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
65:            #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
66:            
67:            // CONFIG7L
68:            #pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
69:            #pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
70:            #pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
71:            #pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
72:            
73:            // CONFIG7H
74:            #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
75:            
76:            // #pragma config statements should precede project file includes.
77:            // Use project enums instead of #define for ON and OFF.
78:            
79:            #define _XTAL_FREQ 64000000
80:            
81:            #include "rs232.h"
82:            #include "midi.h"
83:            
84:            #include <xc.h>
85:            #include <stdio.h>
86:            #include <stdlib.h>
87:            #include <stdint.h>
88:            #include <string.h>
89:            
90:            #define NOTES 16
91:            #define NOTE_MASK 0xFF00
92:            
93:            #define MIDI_CHANNEL 0x0
94:            #define MIDI_SCALE_START 0x3C
95:            
96:            /* global variables */
97:            volatile uint16_t keys_data[NOTES];
98:            volatile uint16_t keypresses = 0; // flags to notify the main program
99:            
100:           /* function prototypes */
101:           int eusart_write_midi(const midi_message_t *pkt);
102:           
103:           /* interrupt service routine */
104:           interrupt void isr(void)
0008  8245     BSF btemp, 1, ACCESS
105:           {
106:               unsigned char i, data_a, data_b;
107:           
108:               PORTDbits.RD3 = 0;
0052  9683     BCF PORTD, 3, ACCESS
109:               
110:               if (PIR1bits.TMR2IF) {
0054  A29E     BTFSS PIR1, 1, ACCESS
0056  D11F     BRA 0x296
111:                   data_a = PORTA;
0058  CF80     MOVFF PORTA, data_a
005A  F03D     NOP
112:                   data_b = PORTB;
005C  CF81     MOVFF PORTB, data_b
005E  F03E     NOP
113:                   i = 7;
0060  0E07     MOVLW 0x7
0062  6E42     MOVWF i, ACCESS
114:                   do {
115:                       // read the data and append it at the end of keys_data[i]
116:                       keys_data[i] = (keys_data[i] << 1) | ((data_a >> i) & 0x01);
0064  5042     MOVF i, W, ACCESS
0066  0D02     MULLW 0x2
0068  0E03     MOVLW 0x3
006A  24F3     ADDWF PROD, W, ACCESS
006C  6ED9     MOVWF FSR2, ACCESS
006E  0E00     MOVLW 0x0
0070  20F4     ADDWFC PRODH, W, ACCESS
0072  6EDA     MOVWF FSR2H, ACCESS
0074  CFDE     MOVFF POSTINC2, __pcstackCOMRAM
0076  F023     NOP
0078  CFDD     MOVFF POSTDEC2, 0x24
007A  F024     NOP
007C  90D8     BCF STATUS, 0, ACCESS
007E  3623     RLCF __pcstackCOMRAM, F, ACCESS
0080  3624     RLCF 0x24, F, ACCESS
0082  C042     MOVFF i, 0x25
0084  F025     NOP
0086  C03D     MOVFF data_a, 0x26
0088  F026     NOP
008A  2A25     INCF 0x25, F, ACCESS
008C  D002     BRA 0x92
008E  90D8     BCF STATUS, 0, ACCESS
0090  3226     RRCF 0x26, F, ACCESS
0092  2E25     DECFSZ 0x25, F, ACCESS
0094  D7FC     BRA 0x8E
0096  0E01     MOVLW 0x1
0098  1626     ANDWF 0x26, F, ACCESS
009A  5026     MOVF 0x26, W, ACCESS
009C  1223     IORWF __pcstackCOMRAM, F, ACCESS
009E  0E00     MOVLW 0x0
00A0  1224     IORWF 0x24, F, ACCESS
00A2  5042     MOVF i, W, ACCESS
00A4  0D02     MULLW 0x2
00A6  0E03     MOVLW 0x3
00A8  24F3     ADDWF PROD, W, ACCESS
00AA  6ED9     MOVWF FSR2, ACCESS
00AC  0E00     MOVLW 0x0
00AE  20F4     ADDWFC PRODH, W, ACCESS
00B0  6EDA     MOVWF FSR2H, ACCESS
00B2  C023     MOVFF __pcstackCOMRAM, POSTINC2
00B4  FFDE     NOP
00B6  C024     MOVFF 0x24, POSTDEC2
00B8  FFDD     NOP
117:                       keys_data[i + 8] = (keys_data[i + 8] << 1) | ((data_b >> i) & 0x01);
00BA  5042     MOVF i, W, ACCESS
00BC  6E23     MOVWF __pcstackCOMRAM, ACCESS
00BE  6A24     CLRF 0x24, ACCESS
00C0  90D8     BCF STATUS, 0, ACCESS
00C2  3623     RLCF __pcstackCOMRAM, F, ACCESS
00C4  3624     RLCF 0x24, F, ACCESS
00C6  0E10     MOVLW 0x10
00C8  2623     ADDWF __pcstackCOMRAM, F, ACCESS
00CA  0E00     MOVLW 0x0
00CC  2224     ADDWFC 0x24, F, ACCESS
00CE  0E03     MOVLW 0x3
00D0  2423     ADDWF __pcstackCOMRAM, W, ACCESS
00D2  6ED9     MOVWF FSR2, ACCESS
00D4  0E00     MOVLW 0x0
00D6  2024     ADDWFC 0x24, W, ACCESS
00D8  6EDA     MOVWF FSR2H, ACCESS
00DA  CFDE     MOVFF POSTINC2, 0x25
00DC  F025     NOP
00DE  CFDD     MOVFF POSTDEC2, 0x26
00E0  F026     NOP
00E2  90D8     BCF STATUS, 0, ACCESS
00E4  3625     RLCF 0x25, F, ACCESS
00E6  3626     RLCF 0x26, F, ACCESS
00E8  C042     MOVFF i, 0x27
00EA  F027     NOP
00EC  C03E     MOVFF data_b, 0x28
00EE  F028     NOP
00F0  2A27     INCF 0x27, F, ACCESS
00F2  D002     BRA 0xF8
00F4  90D8     BCF STATUS, 0, ACCESS
00F6  3228     RRCF 0x28, F, ACCESS
00F8  2E27     DECFSZ 0x27, F, ACCESS
00FA  D7FC     BRA 0xF4
00FC  0E01     MOVLW 0x1
00FE  1628     ANDWF 0x28, F, ACCESS
0100  5028     MOVF 0x28, W, ACCESS
0102  1225     IORWF 0x25, F, ACCESS
0104  0E00     MOVLW 0x0
0106  1226     IORWF 0x26, F, ACCESS
0108  5042     MOVF i, W, ACCESS
010A  6E29     MOVWF 0x29, ACCESS
010C  6A2A     CLRF 0x2A, ACCESS
010E  90D8     BCF STATUS, 0, ACCESS
0110  3629     RLCF 0x29, F, ACCESS
0112  362A     RLCF 0x2A, F, ACCESS
0114  0E10     MOVLW 0x10
0116  2629     ADDWF 0x29, F, ACCESS
0118  0E00     MOVLW 0x0
011A  222A     ADDWFC 0x2A, F, ACCESS
011C  0E03     MOVLW 0x3
011E  2429     ADDWF 0x29, W, ACCESS
0120  6ED9     MOVWF FSR2, ACCESS
0122  0E00     MOVLW 0x0
0124  202A     ADDWFC 0x2A, W, ACCESS
0126  6EDA     MOVWF FSR2H, ACCESS
0128  C025     MOVFF 0x25, POSTINC2
012A  FFDE     NOP
012C  C026     MOVFF 0x26, POSTDEC2
012E  FFDD     NOP
118:           
119:                       // TODO same for PORTD when the steps board is printed
120:                       
121:                       // if the keypress flag is set, the main hasn't sent the packet (yet)
122:                       if (!(keypresses & (1<<i))) {
0130  C042     MOVFF i, __pcstackCOMRAM
0132  F023     NOP
0134  0E01     MOVLW 0x1
0136  6E24     MOVWF 0x24, ACCESS
0138  0E00     MOVLW 0x0
013A  6E25     MOVWF 0x25, ACCESS
013C  2A23     INCF __pcstackCOMRAM, F, ACCESS
013E  D003     BRA 0x146
0140  90D8     BCF STATUS, 0, ACCESS
0142  3624     RLCF 0x24, F, ACCESS
0144  3625     RLCF 0x25, F, ACCESS
0146  2E23     DECFSZ __pcstackCOMRAM, F, ACCESS
0148  D7FB     BRA 0x140
014A  5001     MOVF keypresses, W, ACCESS
014C  1624     ANDWF 0x24, F, ACCESS
014E  5002     MOVF 0x2, W, ACCESS
0150  1625     ANDWF 0x25, F, ACCESS
0152  5024     MOVF 0x24, W, ACCESS
0154  1025     IORWF 0x25, W, ACCESS
0156  A4D8     BTFSS STATUS, 2, ACCESS
0158  D02D     BRA 0x1B4
123:                           // if the flag is not set, check if it should be
124:                           keypresses |= (keys_data[i] && !(keys_data[i] & NOTE_MASK))<<i;
015A  0E00     MOVLW 0x0
015C  6E3F     MOVWF 0x3F, ACCESS
015E  5042     MOVF i, W, ACCESS
0160  0D02     MULLW 0x2
0162  0E03     MOVLW 0x3
0164  24F3     ADDWF PROD, W, ACCESS
0166  6ED9     MOVWF FSR2, ACCESS
0168  0E00     MOVLW 0x0
016A  20F4     ADDWFC PRODH, W, ACCESS
016C  6EDA     MOVWF FSR2H, ACCESS
016E  50DE     MOVF POSTINC2, W, ACCESS
0170  10DE     IORWF POSTINC2, W, ACCESS
0172  B4D8     BTFSC STATUS, 2, ACCESS
0174  D00F     BRA 0x194
0176  5042     MOVF i, W, ACCESS
0178  0D02     MULLW 0x2
017A  0E03     MOVLW 0x3
017C  24F3     ADDWF PROD, W, ACCESS
017E  6ED9     MOVWF FSR2, ACCESS
0180  0E00     MOVLW 0x0
0182  20F4     ADDWFC PRODH, W, ACCESS
0184  6EDA     MOVWF FSR2H, ACCESS
0186  52DE     MOVF POSTINC2, F, ACCESS
0188  0EFF     MOVLW 0xFF
018A  14DD     ANDWF POSTDEC2, W, ACCESS
018C  A4D8     BTFSS STATUS, 2, ACCESS
018E  D002     BRA 0x194
0190  0E01     MOVLW 0x1
0192  6E3F     MOVWF 0x3F, ACCESS
0194  C042     MOVFF i, __pcstackCOMRAM
0196  F023     NOP
0198  503F     MOVF 0x3F, W, ACCESS
019A  6E24     MOVWF 0x24, ACCESS
019C  6A25     CLRF 0x25, ACCESS
019E  2A23     INCF __pcstackCOMRAM, F, ACCESS
01A0  D003     BRA 0x1A8
01A2  90D8     BCF STATUS, 0, ACCESS
01A4  3624     RLCF 0x24, F, ACCESS
01A6  3625     RLCF 0x25, F, ACCESS
01A8  2E23     DECFSZ __pcstackCOMRAM, F, ACCESS
01AA  D7FB     BRA 0x1A2
01AC  5024     MOVF 0x24, W, ACCESS
01AE  1201     IORWF keypresses, F, ACCESS
01B0  5025     MOVF 0x25, W, ACCESS
01B2  1202     IORWF 0x2, F, ACCESS
125:                       }
126:                       
127:                       if (!(keypresses & (1<<(i + 8)))) {
01B4  C042     MOVFF i, __pcstackCOMRAM
01B6  F023     NOP
01B8  0E08     MOVLW 0x8
01BA  2623     ADDWF __pcstackCOMRAM, F, ACCESS
01BC  0E01     MOVLW 0x1
01BE  6E24     MOVWF 0x24, ACCESS
01C0  0E00     MOVLW 0x0
01C2  6E25     MOVWF 0x25, ACCESS
01C4  2A23     INCF __pcstackCOMRAM, F, ACCESS
01C6  D003     BRA 0x1CE
01C8  90D8     BCF STATUS, 0, ACCESS
01CA  3624     RLCF 0x24, F, ACCESS
01CC  3625     RLCF 0x25, F, ACCESS
01CE  2E23     DECFSZ __pcstackCOMRAM, F, ACCESS
01D0  D7FB     BRA 0x1C8
01D2  5001     MOVF keypresses, W, ACCESS
01D4  1624     ANDWF 0x24, F, ACCESS
01D6  5002     MOVF 0x2, W, ACCESS
01D8  1625     ANDWF 0x25, F, ACCESS
01DA  5024     MOVF 0x24, W, ACCESS
01DC  1025     IORWF 0x25, W, ACCESS
01DE  A4D8     BTFSS STATUS, 2, ACCESS
01E0  D03F     BRA 0x260
128:                           keypresses |= (keys_data[i + 8] && !(keys_data[i + 8] & NOTE_MASK))<<(i + 8);
01E2  0E00     MOVLW 0x0
01E4  6E40     MOVWF 0x40, ACCESS
01E6  5042     MOVF i, W, ACCESS
01E8  6E23     MOVWF __pcstackCOMRAM, ACCESS
01EA  6A24     CLRF 0x24, ACCESS
01EC  90D8     BCF STATUS, 0, ACCESS
01EE  3623     RLCF __pcstackCOMRAM, F, ACCESS
01F0  3624     RLCF 0x24, F, ACCESS
01F2  0E10     MOVLW 0x10
01F4  2623     ADDWF __pcstackCOMRAM, F, ACCESS
01F6  0E00     MOVLW 0x0
01F8  2224     ADDWFC 0x24, F, ACCESS
01FA  0E03     MOVLW 0x3
01FC  2423     ADDWF __pcstackCOMRAM, W, ACCESS
01FE  6ED9     MOVWF FSR2, ACCESS
0200  0E00     MOVLW 0x0
0202  2024     ADDWFC 0x24, W, ACCESS
0204  6EDA     MOVWF FSR2H, ACCESS
0206  50DE     MOVF POSTINC2, W, ACCESS
0208  10DE     IORWF POSTINC2, W, ACCESS
020A  B4D8     BTFSC STATUS, 2, ACCESS
020C  D017     BRA 0x23C
020E  5042     MOVF i, W, ACCESS
0210  6E23     MOVWF __pcstackCOMRAM, ACCESS
0212  6A24     CLRF 0x24, ACCESS
0214  90D8     BCF STATUS, 0, ACCESS
0216  3623     RLCF __pcstackCOMRAM, F, ACCESS
0218  3624     RLCF 0x24, F, ACCESS
021A  0E10     MOVLW 0x10
021C  2623     ADDWF __pcstackCOMRAM, F, ACCESS
021E  0E00     MOVLW 0x0
0220  2224     ADDWFC 0x24, F, ACCESS
0222  0E03     MOVLW 0x3
0224  2423     ADDWF __pcstackCOMRAM, W, ACCESS
0226  6ED9     MOVWF FSR2, ACCESS
0228  0E00     MOVLW 0x0
022A  2024     ADDWFC 0x24, W, ACCESS
022C  6EDA     MOVWF FSR2H, ACCESS
022E  52DE     MOVF POSTINC2, F, ACCESS
0230  0EFF     MOVLW 0xFF
0232  14DD     ANDWF POSTDEC2, W, ACCESS
0234  A4D8     BTFSS STATUS, 2, ACCESS
0236  D002     BRA 0x23C
0238  0E01     MOVLW 0x1
023A  6E40     MOVWF 0x40, ACCESS
023C  C042     MOVFF i, __pcstackCOMRAM
023E  F023     NOP
0240  0E08     MOVLW 0x8
0242  2623     ADDWF __pcstackCOMRAM, F, ACCESS
0244  5040     MOVF 0x40, W, ACCESS
0246  6E24     MOVWF 0x24, ACCESS
0248  6A25     CLRF 0x25, ACCESS
024A  2A23     INCF __pcstackCOMRAM, F, ACCESS
024C  D003     BRA 0x254
024E  90D8     BCF STATUS, 0, ACCESS
0250  3624     RLCF 0x24, F, ACCESS
0252  3625     RLCF 0x25, F, ACCESS
0254  2E23     DECFSZ __pcstackCOMRAM, F, ACCESS
0256  D7FB     BRA 0x24E
0258  5024     MOVF 0x24, W, ACCESS
025A  1201     IORWF keypresses, F, ACCESS
025C  5025     MOVF 0x25, W, ACCESS
025E  1202     IORWF 0x2, F, ACCESS
129:                       }
130:                   } while (i--);
0260  0642     DECF i, F, ACCESS
0262  2842     INCF i, W, ACCESS
0264  A4D8     BTFSS STATUS, 2, ACCESS
0266  D6FE     BRA 0x64
131:                   
132:                   
133:                   // debug stuff
134:                   PORTDbits.RD4 = PORTAbits.RA0;
0268  A080     BTFSS PORTA, 0, ACCESS
026A  D002     BRA 0x270
026C  8883     BSF PORTD, 4, ACCESS
026E  D001     BRA 0x272
0270  9883     BCF PORTD, 4, ACCESS
135:                   PORTDbits.RD2 = (keys_data[0] && !(keys_data[0] & NOTE_MASK));
0272  0E00     MOVLW 0x0
0274  6E41     MOVWF 0x41, ACCESS
0276  5003     MOVF keys_data, W, ACCESS
0278  1004     IORWF 0x4, W, ACCESS
027A  B4D8     BTFSC STATUS, 2, ACCESS
027C  D006     BRA 0x28A
027E  0EFF     MOVLW 0xFF
0280  1404     ANDWF 0x4, W, ACCESS
0282  A4D8     BTFSS STATUS, 2, ACCESS
0284  D002     BRA 0x28A
0286  0E01     MOVLW 0x1
0288  6E41     MOVWF 0x41, ACCESS
028A  B041     BTFSC 0x41, 0, ACCESS
028C  D002     BRA 0x292
028E  9483     BCF PORTD, 2, ACCESS
0290  D001     BRA 0x294
0292  8483     BSF PORTD, 2, ACCESS
136:           
137:                   // reset interrupt flag
138:                   PIR1bits.TMR2IF = 0;
0294  929E     BCF PIR1, 1, ACCESS
139:               }
140:               
141:               PORTDbits.RD3 = 1;
0296  8683     BSF PORTD, 3, ACCESS
142:           }
0298  C03C     MOVFF 0x3C, 0x48
029A  F048     NOP
029C  C03B     MOVFF 0x3B, 0x47
029E  F047     NOP
02A0  C03A     MOVFF 0x3A, 0x46
02A2  F046     NOP
02A4  C039     MOVFF 0x39, btemp
02A6  F045     NOP
02A8  C038     MOVFF 0x38, TABLAT
02AA  FFF5     NOP
02AC  C037     MOVFF 0x37, TBLPTRU
02AE  FFF8     NOP
02B0  C036     MOVFF 0x36, TBLPTRH
02B2  FFF7     NOP
02B4  C035     MOVFF 0x35, TBLPTR
02B6  FFF6     NOP
02B8  C034     MOVFF 0x34, PRODH
02BA  FFF4     NOP
02BC  C033     MOVFF 0x33, PROD
02BE  FFF3     NOP
02C0  C032     MOVFF 0x32, FSR2H
02C2  FFDA     NOP
02C4  C031     MOVFF 0x31, FSR2
02C6  FFD9     NOP
02C8  C030     MOVFF 0x30, FSR1H
02CA  FFE2     NOP
02CC  C02F     MOVFF 0x2F, FSR1
02CE  FFE1     NOP
02D0  C02E     MOVFF 0x2E, FSR0H
02D2  FFEA     NOP
02D4  C02D     MOVFF 0x2D, FSR0
02D6  FFE9     NOP
02D8  C02C     MOVFF 0x2C, PCLATU
02DA  FFFB     NOP
02DC  C02B     MOVFF 0x2B, PCLATH
02DE  FFFA     NOP
02E0  9245     BCF btemp, 1, ACCESS
02E2  0011     RETFIE 1
143:           
144:           /* hardware configuration (inlined) */
145:           inline void init_hw(void)
146:           {
147:               di();
048A  9EF2     BCF INTCON, 7, ACCESS
148:               
149:               /* PLL / FOSC configuration */
150:               // enable PLL
151:               OSCTUNEbits.PLLEN = 1;
048C  8C9B     BSF OSCTUNE, 6, ACCESS
152:               // set FOSC to HFINTOSC (max frequency)
153:               OSCTUNEbits.TUN = 0b011111;
048E  809B     BSF OSCTUNE, 0, ACCESS
0490  829B     BSF OSCTUNE, 1, ACCESS
0492  849B     BSF OSCTUNE, 2, ACCESS
0494  869B     BSF OSCTUNE, 3, ACCESS
0496  889B     BSF OSCTUNE, 4, ACCESS
0498  9A9B     BCF OSCTUNE, 5, ACCESS
154:               // set 16 MHz oscillator, datasheet p.30
155:               OSCCONbits.IRCF = 0b111;
049A  88D3     BSF OSCCON, 4, ACCESS
049C  8AD3     BSF OSCCON, 5, ACCESS
049E  8CD3     BSF OSCCON, 6, ACCESS
156:               // select primary clock (with PLL)
157:               OSCCONbits.SCS = 0b00;
04A0  0EFC     MOVLW 0xFC
04A2  16D3     ANDWF OSCCON, F, ACCESS
158:               
159:               /* i/o initializazion */
160:               // disable all ADCs
161:               ANSELA = 0x00;
04A4  0E00     MOVLW 0x0
04A6  010F     MOVLB 0xF
04A8  6F38     MOVWF 0x38, BANKED
162:               ANSELB = 0x00;
04AA  0E00     MOVLW 0x0
04AC  6F39     MOVWF 0x39, BANKED
163:               ANSELC = 0x00;
04AE  0E00     MOVLW 0x0
04B0  6F3A     MOVWF 0x3A, BANKED
164:               ANSELD = 0x00;
04B2  0E00     MOVLW 0x0
04B4  6F3B     MOVWF 0x3B, BANKED
165:           
166:               // TODO: remove demo
167:               TRISA = 0xFF;
04B6  6892     SETF TRISA, ACCESS
168:               TRISB = 0xFF;
04B8  6893     SETF TRISB, ACCESS
169:               
170:               TRISDbits.TRISD1 = 0;
04BA  9295     BCF TRISD, 1, ACCESS
171:               TRISDbits.TRISD2 = 0;
04BC  9495     BCF TRISD, 2, ACCESS
172:               TRISDbits.TRISD3 = 0;
04BE  9695     BCF TRISD, 3, ACCESS
173:               TRISDbits.TRISD4 = 0;
04C0  9895     BCF TRISD, 4, ACCESS
174:               
175:               // LED
176:               PORTDbits.RD1 = 1;
04C2  8283     BSF PORTD, 1, ACCESS
177:               // TEST OUTPUT 1
178:               PORTDbits.RD2 = 0;
04C4  9483     BCF PORTD, 2, ACCESS
179:               // TEST OUTPUT 2
180:               PORTDbits.RD3 = 1;
04C6  8683     BSF PORTD, 3, ACCESS
181:               // TEST OUTPUT 3
182:               PORTDbits.RD4 = 0;
04C8  9883     BCF PORTD, 4, ACCESS
183:           
184:               /* timer configuration */
185:               // timer 2 comp value
186:               PR2 = 128;
04CA  0E80     MOVLW 0x80
04CC  6EBB     MOVWF PR2, ACCESS
187:               // postscaler 1:4
188:               T2CONbits.T2OUTPS = 0b0011;
04CE  50BA     MOVF T2CON, W, ACCESS
04D0  0B87     ANDLW 0x87
04D2  0918     IORLW 0x18
04D4  6EBA     MOVWF T2CON, ACCESS
189:               // prescaler 1:16
190:               T2CONbits.T2CKPS = 0b11;
04D6  0E03     MOVLW 0x3
04D8  12BA     IORWF T2CON, F, ACCESS
191:               // start timer
192:               T2CONbits.TMR2ON = 1;
04DA  84BA     BSF T2CON, 2, ACCESS
193:               
194:               // timer 2 interrupts
195:               PIE1bits.TMR2IE = 1;
04DC  829D     BSF PIE1, 1, ACCESS
196:               PIR1bits.TMR2IF = 0;
04DE  929E     BCF PIR1, 1, ACCESS
197:           
198:               // enable peripheral interrupts
199:               INTCONbits.PEIE = 1;
04E0  8CF2     BSF INTCON, 6, ACCESS
200:               
201:               /* serial configuration */
202:               eusart1_init();
04E2  ECCC     CALL 0x598, 0
04E4  F002     NOP
203:           }
04E6  0012     RETURN 0
204:           
205:           
206:           /* main program */
207:           void main(void)
208:           {
209:               uint8_t i;
210:               midi_message_t message;
211:               
212:               /* setup hardware */
213:               init_hw();
02E8  EC45     CALL 0x48A, 0
02EA  F002     NOP
214:              
215:               /* setup software */
216:               memset(keys_data, 0, sizeof(keys_data));
02EC  0E03     MOVLW 0x3
02EE  0100     MOVLB 0x0
02F0  6F60     MOVWF __pcstackBANK0, BANKED
02F2  0E00     MOVLW 0x0
02F4  6F61     MOVWF pkt, BANKED
02F6  0E00     MOVLW 0x0
02F8  6F63     MOVWF 0x63, BANKED
02FA  0E00     MOVLW 0x0
02FC  6F62     MOVWF c, BANKED
02FE  0E00     MOVLW 0x0
0300  6F65     MOVWF pkt, BANKED
0302  0E20     MOVLW 0x20
0304  6F64     MOVWF n, BANKED
0306  EC8D     CALL 0x51A, 0
0308  F002     NOP
217:               
218:               ei();
030A  8EF2     BSF INTCON, 7, ACCESS
219:               
220:               /* TODO remove demo code */
221:               PORTDbits.RD1 = 0;
030C  9283     BCF PORTD, 1, ACCESS
222:           
223:               midi_note_on(&message, MIDI_CHANNEL, MIDI_SCALE_START, 0x7F);
030E  0E71     MOVLW 0x71
0310  0100     MOVLB 0x0
0312  6F65     MOVWF pkt, BANKED
0314  0E00     MOVLW 0x0
0316  6F66     MOVWF p, BANKED
0318  0E00     MOVLW 0x0
031A  6F68     MOVWF 0x68, BANKED
031C  0E00     MOVLW 0x0
031E  6F67     MOVWF channel, BANKED
0320  0E3C     MOVLW 0x3C
0322  6F69     MOVWF note, BANKED
0324  0E7F     MOVLW 0x7F
0326  6F6A     MOVWF velocity, BANKED
0328  EC12     CALL 0x424, 0
032A  F002     NOP
224:               
225:               /* main loop */
226:               while (1) {
227:                   // check flags
228:                   for (i = 0; i < NOTES; i++) {
032C  0E00     MOVLW 0x0
032E  0100     MOVLB 0x0
0330  6F70     MOVWF i, BANKED
0332  0E0F     MOVLW 0xF
0334  6570     CPFSGT i, BANKED
0336  D001     BRA 0x33A
0338  D7F9     BRA 0x32C
229:                       if (keypresses & (1<<i)) {
033A  C070     MOVFF i, 0x6B
033C  F06B     NOP
033E  0E01     MOVLW 0x1
0340  6F6C     MOVWF 0x6C, BANKED
0342  0E00     MOVLW 0x0
0344  6F6D     MOVWF 0x6D, BANKED
0346  2B6B     INCF 0x6B, F, BANKED
0348  D003     BRA 0x350
034A  90D8     BCF STATUS, 0, ACCESS
034C  376C     RLCF 0x6C, F, BANKED
034E  376D     RLCF 0x6D, F, BANKED
0350  2F6B     DECFSZ 0x6B, F, BANKED
0352  D7FB     BRA 0x34A
0354  5001     MOVF keypresses, W, ACCESS
0356  0100     MOVLB 0x0
0358  176C     ANDWF 0x6C, F, BANKED
035A  5002     MOVF 0x2, W, ACCESS
035C  176D     ANDWF 0x6D, F, BANKED
035E  516C     MOVF 0x6C, W, BANKED
0360  116D     IORWF 0x6D, W, BANKED
0362  B4D8     BTFSC STATUS, 2, ACCESS
0364  D020     BRA 0x3A6
230:                           
231:                           message.data[0] = MIDI_SCALE_START + i;
0366  5170     MOVF i, W, BANKED
0368  0F3C     ADDLW 0x3C
036A  6F74     MOVWF 0x74, BANKED
232:                           // midi_note_on(&message, MIDI_CHANNEL, MIDI_SCALE_START + i, 0x7F);
233:           
234:                           eusart_write_midi(&message);
036C  0E71     MOVLW 0x71
036E  6F61     MOVWF pkt, BANKED
0370  0E00     MOVLW 0x0
0372  6F62     MOVWF c, BANKED
0374  ECD5     CALL 0x3AA, 0
0376  F001     NOP
235:                           
236:                           // unset flag
237:                           keypresses &= ~(1<<i);
0378  C070     MOVFF i, 0x6B
037A  F06B     NOP
037C  0E01     MOVLW 0x1
037E  0100     MOVLB 0x0
0380  6F6C     MOVWF 0x6C, BANKED
0382  0E00     MOVLW 0x0
0384  6F6D     MOVWF 0x6D, BANKED
0386  2B6B     INCF 0x6B, F, BANKED
0388  D003     BRA 0x390
038A  90D8     BCF STATUS, 0, ACCESS
038C  376C     RLCF 0x6C, F, BANKED
038E  376D     RLCF 0x6D, F, BANKED
0390  2F6B     DECFSZ 0x6B, F, BANKED
0392  D7FB     BRA 0x38A
0394  0100     MOVLB 0x0
0396  1D6C     COMF 0x6C, W, BANKED
0398  6F6E     MOVWF 0x6E, BANKED
039A  1D6D     COMF 0x6D, W, BANKED
039C  6F6F     MOVWF 0x6F, BANKED
039E  516E     MOVF 0x6E, W, BANKED
03A0  1601     ANDWF keypresses, F, ACCESS
03A2  516F     MOVF 0x6F, W, BANKED
03A4  1602     ANDWF 0x2, F, ACCESS
238:                       }
03A6  2B70     INCF i, F, BANKED
03A8  D7C4     BRA 0x332
239:                   }
240:               }
241:           }
242:           
243:           
244:           int eusart_write_midi(const midi_message_t *pkt)
245:           {
246:               size_t length;
247:               uint8_t *data;
248:               
249:               if (pkt == NULL) {
03AA  0100     MOVLB 0x0
03AC  5161     MOVF pkt, W, BANKED
03AE  1162     IORWF c, W, BANKED
03B0  B4D8     BTFSC STATUS, 2, ACCESS
03B2  0012     RETURN 0
250:                   return -1;
251:               }
252:               
253:               length = pkt->data_size;
03B4  EE20     LFSR 2, 0x1
03B6  F001     NOP
03B8  5161     MOVF pkt, W, BANKED
03BA  26D9     ADDWF FSR2, F, ACCESS
03BC  5162     MOVF c, W, BANKED
03BE  22DA     ADDWFC FSR2H, F, ACCESS
03C0  CFDE     MOVFF POSTINC2, pkt
03C2  F065     NOP
03C4  CFDD     MOVFF POSTDEC2, p
03C6  F066     NOP
254:               data = (uint8_t *) pkt->data;
03C8  0E03     MOVLW 0x3
03CA  2561     ADDWF pkt, W, BANKED
03CC  6F67     MOVWF channel, BANKED
03CE  0E00     MOVLW 0x0
03D0  2162     ADDWFC c, W, BANKED
03D2  6F68     MOVWF 0x68, BANKED
255:               
256:               putch((char)((pkt->status << 4) | pkt->channel));
03D4  C061     MOVFF pkt, FSR2
03D6  FFD9     NOP
03D8  C062     MOVFF c, FSR2H
03DA  FFDA     NOP
03DC  38DF     SWAPF INDF2, W, ACCESS
03DE  0B0F     ANDLW 0xF
03E0  6F63     MOVWF 0x63, BANKED
03E2  C061     MOVFF pkt, FSR2
03E4  FFD9     NOP
03E6  C062     MOVFF c, FSR2H
03E8  FFDA     NOP
03EA  50DF     MOVF INDF2, W, ACCESS
03EC  0B0F     ANDLW 0xF
03EE  6F64     MOVWF n, BANKED
03F0  3964     SWAPF n, W, BANKED
03F2  0BF0     ANDLW 0xF0
03F4  1163     IORWF 0x63, W, BANKED
03F6  ECDA     CALL 0x5B4, 0
03F8  F002     NOP
257:               
258:               while (length--) {
03FA  D00A     BRA 0x410
259:                   putch((char) *(data++));
03FC  C067     MOVFF channel, FSR2
03FE  FFD9     NOP
0400  C068     MOVFF 0x68, FSR2H
0402  FFDA     NOP
0404  50DF     MOVF INDF2, W, ACCESS
0406  ECDA     CALL 0x5B4, 0
0408  F002     NOP
040A  0100     MOVLB 0x0
040C  4B67     INFSNZ channel, F, BANKED
040E  2B68     INCF 0x68, F, BANKED
260:               }
0410  0100     MOVLB 0x0
0412  0765     DECF pkt, F, BANKED
0414  A0D8     BTFSS STATUS, 0, ACCESS
0416  0766     DECF p, F, BANKED
0418  2965     INCF pkt, W, BANKED
041A  E1F0     BNZ 0x3FC
041C  2966     INCF p, W, BANKED
041E  B4D8     BTFSC STATUS, 2, ACCESS
0420  0012     RETURN 0
0422  D7EC     BRA 0x3FC
261:               
262:               return 0;
263:           }
---  C:/Program Files/Microchip/xc8/v1.44/sources/common/memset.c  --------------------------------------
1:             #include	<string.h>
2:             
3:             #ifdef _PIC16
4:             far void *
5:             memset(far void * p1, int c, register size_t n)
6:             #else /*  _PIC16 */
7:             void *
8:             memset(void * p1, int c, register size_t n)
9:             #endif /* _PIC16 */
10:            {
11:            
12:            #ifdef _PIC16
13:            	register far char *	p;
14:            #else /*  _PIC16 */
15:            	register char *		p;
16:            #endif /* _PIC16 */
17:            
18:            	p = p1;
051A  C060     MOVFF __pcstackBANK0, p
051C  F066     NOP
051E  C061     MOVFF pkt, channel
0520  F067     NOP
19:            	while(n--)
0522  D009     BRA 0x536
0536  0100     MOVLB 0x0
20:            		*p++ = c;
0524  C066     MOVFF p, FSR2
0526  FFD9     NOP
0528  C067     MOVFF channel, FSR2H
052A  FFDA     NOP
052C  C062     MOVFF c, INDF2
052E  FFDF     NOP
0530  0100     MOVLB 0x0
0532  4B66     INFSNZ p, F, BANKED
0534  2B67     INCF channel, F, BANKED
0536  0100     MOVLB 0x0
0538  0764     DECF n, F, BANKED
053A  A0D8     BTFSS STATUS, 0, ACCESS
053C  0765     DECF pkt, F, BANKED
053E  2964     INCF n, W, BANKED
0540  E1F1     BNZ 0x524
0542  2965     INCF pkt, W, BANKED
0544  B4D8     BTFSC STATUS, 2, ACCESS
0546  0012     RETURN 0
0548  D7ED     BRA 0x524
21:            	return p1;
22:            }