path: root/src/disassembly/listing.disasm

Disassembly Listing for Xilofono
Generated From:
Z:/SAMB_4/projects/xilofono/src/dist/default/production/src.production.elf
23-feb-2018 16:30:03

---  Z:/SAMB_4/projects/xilofono/src/rs232.c  -----------------------------------------------------------
1:             #include "rs232.h"
2:             #include <xc.h>
3:             
4:             void eusart1_init(void)
5:             {
6:                 // set Async and 8 bits frame
7:                 TXSTA1bits.SYNC = 0;
03FC  98AC     BCF TXSTA1, 4, ACCESS
8:                 TXSTA1bits.TX9 = 0;
03FE  9CAC     BCF TXSTA1, 6, ACCESS
9:                 
10:                // baud prescaler
11:                RCSTA1bits.SPEN = 1;
0400  8EAB     BSF RCSTA1, 7, ACCESS
12:                SPBRG1 = 31;
0402  0E1F     MOVLW 0x1F
0404  6EAF     MOVWF SPBRG1, ACCESS
13:                SPBRGH1 = 0;
0406  0E00     MOVLW 0x0
0408  6EB0     MOVWF SPBRGH1, ACCESS
14:                TXSTA1bits.BRGH = 0;
040A  94AC     BCF TXSTA1, 2, ACCESS
15:                BAUDCON1bits.BRG16 = 0;
040C  96B8     BCF BAUDCON1, 3, ACCESS
16:                
17:                // set up TX / RX pins
18:                TRISCbits.TRISC7 = 1;
040E  8E94     BSF TRISC, 7, ACCESS
19:                TRISCbits.TRISC6 = 1;
0410  8C94     BSF TRISC, 6, ACCESS
20:                RCSTA1bits.CREN = 1; // enable continuous reception
0412  88AB     BSF RCSTA1, 4, ACCESS
21:                TXSTA1bits.TXEN = 1;
0414  8AAC     BSF TXSTA1, 5, ACCESS
22:            }
0416  0012     RETURN 0
23:            
24:            void eusart2_init(void)
25:            {
26:                // TODO
27:            }
28:            
29:            void putch(char c)
0418  6E1A     MOVWF p1, ACCESS
30:            {
31:                while (!TX1IF);
041A  A89E     BTFSS PIR1, 4, ACCESS
041C  D7FE     BRA 0x41A
32:                TX1REG = c;
041E  C01A     MOVFF p1, TXREG1
0420  FFAD     NOP
33:            }
0008  8245     BSF btemp, 1, ACCESS
000A  CFFA     MOVFF PCLATH, 0x5
000C  F005     NOP
000E  CFFB     MOVFF PCLATU, 0x6
0010  F006     NOP
0012  CFE9     MOVFF FSR0, 0x7
0014  F007     NOP
0016  CFEA     MOVFF FSR0H, 0x8
0018  F008     NOP
001A  CFE1     MOVFF FSR1, 0x9
001C  F009     NOP
001E  CFE2     MOVFF FSR1H, 0xA
0020  F00A     NOP
0022  CFD9     MOVFF FSR2, 0xB
0024  F00B     NOP
0026  CFDA     MOVFF FSR2H, 0xC
0028  F00C     NOP
002A  CFF3     MOVFF PROD, 0xD
002C  F00D     NOP
002E  CFF4     MOVFF PRODH, 0xE
0030  F00E     NOP
0032  CFF6     MOVFF TBLPTR, 0xF
0034  F00F     NOP
0036  CFF7     MOVFF TBLPTRH, 0x10
0038  F010     NOP
003A  CFF8     MOVFF TBLPTRU, 0x11
003C  F011     NOP
003E  CFF5     MOVFF TABLAT, 0x12
0040  F012     NOP
0042  C045     MOVFF btemp, 0x13
0044  F013     NOP
0046  C046     MOVFF 0x46, 0x14
0048  F014     NOP
004A  C047     MOVFF 0x47, 0x15
004C  F015     NOP
004E  C048     MOVFF 0x48, 0x16
0050  F016     NOP
0422  0012     RETURN 0
34:            
35:            char getch(void)
36:            {
37:                while (!RC1IF);
38:                return RC1REG;
39:            }
40:            
41:            char getche(void)
42:            {
43:                char c = getch();
44:                putch(c); // echo
45:                
46:                return c;
47:            }
---  Z:/SAMB_4/projects/xilofono/src/midi.c  ------------------------------------------------------------
1:             #include "midi.h"
2:             
3:             #include <stdint.h>
4:             #include <stddef.h>
5:             #include <stdio.h>
6:             #include <stdlib.h>
7:             
8:             
9:             #ifdef MIDI_DYNAMIC_MEMORY_ALLOC
10:            midi_message_t *midi_alloc_message(size_t data_size)
11:            {
12:                return (midi_message_t *) malloc(sizeof(midi_message_t) + data_size);
13:            }
14:            
15:            void midi_free_message(midi_message_t *pkt)
16:            {
17:                if (pkt == NULL) {
18:                    return;
19:                }
20:                
21:                free(pkt);
22:                pkt = NULL;
23:            }
24:            
25:            size_t midi_message_size(const midi_message_t *pkt)
26:            {
27:                if (pkt == NULL) {
28:                    return 0;   
29:                }
30:                
31:                switch (pkt->status) {
32:                    case NOTE_ON:  return sizeof(midi_message_t) + 2;
33:                    case NOTE_OFF: return sizeof(midi_message_t) + 1;
34:                    default:       return sizeof(midi_message_t);
35:                }
36:            }
37:            #endif
38:            
39:            
40:            int midi_set_status(midi_message_t *pkt, midi_status_t status)
41:            {
42:                if (pkt == NULL) {
03D8  501A     MOVF p1, W, ACCESS
03DA  101B     IORWF pkt, W, ACCESS
03DC  B4D8     BTFSC STATUS, 2, ACCESS
03DE  0012     RETURN 0
43:                    return -1;
44:                }
45:                
46:                pkt->status = status & 0x0F;
03E0  C01C     MOVFF c, 0x1D
03E2  F01D     NOP
03E4  0E0F     MOVLW 0xF
03E6  161D     ANDWF 0x1D, F, ACCESS
03E8  C01A     MOVFF p1, FSR2
03EA  FFD9     NOP
03EC  C01B     MOVFF pkt, FSR2H
03EE  FFDA     NOP
03F0  50DF     MOVF INDF2, W, ACCESS
03F2  181D     XORWF 0x1D, W, ACCESS
03F4  0BF0     ANDLW 0xF0
03F6  181D     XORWF 0x1D, W, ACCESS
03F8  6EDF     MOVWF INDF2, ACCESS
03FA  0012     RETURN 0
47:                
48:                return 0;
49:            }
50:            
51:            int midi_set_channel(midi_message_t *pkt, unsigned channel)
52:            {
53:                if (pkt == NULL) {
03B2  501A     MOVF p1, W, ACCESS
03B4  101B     IORWF pkt, W, ACCESS
03B6  B4D8     BTFSC STATUS, 2, ACCESS
03B8  0012     RETURN 0
54:                    return -1;
55:                }
56:                
57:                pkt->channel = channel & 0x0F;
03BA  C01C     MOVFF c, n
03BC  F01E     NOP
03BE  0E0F     MOVLW 0xF
03C0  161E     ANDWF n, F, ACCESS
03C2  C01A     MOVFF p1, FSR2
03C4  FFD9     NOP
03C6  C01B     MOVFF pkt, FSR2H
03C8  FFDA     NOP
03CA  3A1E     SWAPF n, F, ACCESS
03CC  50DF     MOVF INDF2, W, ACCESS
03CE  181E     XORWF n, W, ACCESS
03D0  0B0F     ANDLW 0xF
03D2  181E     XORWF n, W, ACCESS
03D4  6EDF     MOVWF INDF2, ACCESS
03D6  0012     RETURN 0
58:                
59:                return 0;
60:            }
61:            
62:            int midi_note_on(midi_message_t *pkt, unsigned channel, midi_note_t note, uint8_t velocity)
63:            {
64:                if (pkt == NULL) {
01BC  501F     MOVF pkt, W, ACCESS
01BE  1020     IORWF p, W, ACCESS
01C0  B4D8     BTFSC STATUS, 2, ACCESS
01C2  0012     RETURN 0
65:                    return -1;
66:                }
67:                
68:                if (pkt->data == NULL) {
01C4  0E03     MOVLW 0x3
01C6  241F     ADDWF pkt, W, ACCESS
01C8  0100     MOVLB 0x0
01CA  6F60     MOVWF __pcstackBANK0, BANKED
01CC  0E00     MOVLW 0x0
01CE  2020     ADDWFC p, W, ACCESS
01D0  6F61     MOVWF 0x61, BANKED
01D2  5160     MOVF __pcstackBANK0, W, BANKED
01D4  1161     IORWF 0x61, W, BANKED
01D6  B4D8     BTFSC STATUS, 2, ACCESS
01D8  0012     RETURN 0
69:                    return -2;
70:                }
71:                
72:                midi_set_status(pkt, NOTE_ON);
01DA  C01F     MOVFF pkt, p1
01DC  F01A     NOP
01DE  C020     MOVFF p, pkt
01E0  F01B     NOP
01E2  0E08     MOVLW 0x8
01E4  6E1C     MOVWF c, ACCESS
01E6  ECEC     CALL 0x3D8, 0
01E8  F001     NOP
73:                midi_set_channel(pkt, channel);
01EA  C01F     MOVFF pkt, p1
01EC  F01A     NOP
01EE  C020     MOVFF p, pkt
01F0  F01B     NOP
01F2  C021     MOVFF channel, c
01F4  F01C     NOP
01F6  C022     MOVFF 0x22, 0x1D
01F8  F01D     NOP
01FA  ECD9     CALL 0x3B2, 0
01FC  F001     NOP
74:                
75:                pkt->data[0] = note;
01FE  EE20     LFSR 2, 0x3
0200  F003     NOP
0202  501F     MOVF pkt, W, ACCESS
0204  26D9     ADDWF FSR2, F, ACCESS
0206  5020     MOVF p, W, ACCESS
0208  22DA     ADDWFC FSR2H, F, ACCESS
020A  C023     MOVFF note, INDF2
020C  FFDF     NOP
76:                pkt->data[1] = velocity;
020E  EE20     LFSR 2, 0x4
0210  F004     NOP
0212  501F     MOVF pkt, W, ACCESS
0214  26D9     ADDWF FSR2, F, ACCESS
0216  5020     MOVF p, W, ACCESS
0218  22DA     ADDWFC FSR2H, F, ACCESS
021A  C024     MOVFF velocity, INDF2
021C  FFDF     NOP
77:                
78:            #ifndef MIDI_DYNAMIC_MEMORY_ALLOC
79:                pkt->data_size = 2;
021E  EE20     LFSR 2, 0x1
0220  F001     NOP
0222  501F     MOVF pkt, W, ACCESS
0224  26D9     ADDWF FSR2, F, ACCESS
0226  5020     MOVF p, W, ACCESS
0228  22DA     ADDWFC FSR2H, F, ACCESS
022A  0E02     MOVLW 0x2
022C  6EDE     MOVWF POSTINC2, ACCESS
022E  0E00     MOVLW 0x0
0230  6EDD     MOVWF POSTDEC2, ACCESS
0232  0012     RETURN 0
80:            #endif
81:                
82:                return 0;
83:            }
84:            
85:            int midi_note_off(midi_message_t *pkt, unsigned channel, midi_note_t note, uint8_t velocity)
86:            {
87:                if (pkt == NULL) {
88:                    return -1;
89:                }
90:                
91:                if (pkt->data == NULL) {
92:                    return -2;
93:                }
94:                
95:                midi_set_status(pkt, NOTE_OFF);
96:                midi_set_channel(pkt, channel);
97:                
98:                pkt->data[0] = note;
99:                pkt->data[1] = velocity;
100:               
101:           #ifndef MIDI_DYNAMIC_MEMORY_ALLOC
102:               pkt->data_size = 2;
103:           #endif
104:               
105:               return 0;
106:           }
---  Z:/SAMB_4/projects/xilofono/src/main.c  ------------------------------------------------------------
1:             /*
2:              * File:    main.c
3:              * Author:  Naoki Pross 4E
4:              * Date:    08.01.2018
5:              * Target:  PIC18F44K22
6:              * Version  1.0
7:              * 
8:              * Description:
9:              * 
10:             * Main program for the Xylophone project.
11:             */
12:            
13:            // PIC18F44K22 Configuration Bit Settings
14:            // 'C' source line config statements
15:            
16:            // CONFIG1H
17:            #pragma config FOSC = INTIO7    // Oscillator Selection bits (Internal oscillator block)
18:            #pragma config PLLCFG = ON      // 4X PLL Enable (Oscillator multiplied by 4)
19:            #pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock is always enabled)
20:            #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
21:            #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
22:            
23:            // CONFIG2L
24:            #pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer disabled)
25:            #pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
26:            #pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
27:            
28:            // CONFIG2H
29:            #pragma config WDTEN = ON       // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
30:            #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
31:            
32:            // CONFIG3H
33:            #pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
34:            #pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
35:            #pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
36:            #pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
37:            #pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
38:            #pragma config P2BMX = PORTD2   // ECCP2 B output mux bit (P2B is on RD2)
39:            #pragma config MCLRE = EXTMCLR  // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
40:            
41:            // CONFIG4L
42:            #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
43:            #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
44:            #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
45:            
46:            // CONFIG5L
47:            #pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
48:            #pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
49:            #pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
50:            #pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
51:            
52:            // CONFIG5H
53:            #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
54:            #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
55:            
56:            // CONFIG6L
57:            #pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
58:            #pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
59:            #pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
60:            #pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
61:            
62:            // CONFIG6H
63:            #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
64:            #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
65:            #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
66:            
67:            // CONFIG7L
68:            #pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
69:            #pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
70:            #pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
71:            #pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
72:            
73:            // CONFIG7H
74:            #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
75:            
76:            // #pragma config statements should precede project file includes.
77:            // Use project enums instead of #define for ON and OFF.
78:            
79:            #define _XTAL_FREQ 64000000
80:            
81:            #include "rs232.h"
82:            #include "midi.h"
83:            
84:            #include <xc.h>
85:            #include <stdio.h>
86:            #include <stdlib.h>
87:            #include <stdint.h>
88:            #include <string.h>
89:            
90:            #define NOTES 15 
91:            #define NOTE_MASK 0xFF00
92:            
93:            
94:            /* global variables */
95:            volatile uint16_t keypresses[NOTES];
96:            
97:            /* function prototypes */
98:            int eusart_write_midi(const midi_message_t *pkt);
99:            
100:           /* interrupt service routine */
101:           interrupt void isr(void)
0008  8245     BSF btemp, 1, ACCESS
102:           {
103:               unsigned char i, data;
104:           
105:               PORTDbits.RD3 = 0;
0052  9683     BCF PORTD, 3, ACCESS
106:               
107:               if (PIR1bits.TMR2IF) {
0054  A29E     BTFSS PIR1, 1, ACCESS
0056  D089     BRA 0x16A
108:                   // PORTA
109:                   data = PORTA;
0058  CF80     MOVFF PORTA, data
005A  F018     NOP
110:                   i = 7;
005C  0E07     MOVLW 0x7
005E  6E19     MOVWF i, ACCESS
111:                   do {
112:                       keypresses[i] = (keypresses[i] << 1) | ((data >> i) & 0x01);
0060  5019     MOVF i, W, ACCESS
0062  0D02     MULLW 0x2
0064  0E25     MOVLW 0x25
0066  24F3     ADDWF PROD, W, ACCESS
0068  6ED9     MOVWF FSR2, ACCESS
006A  0E00     MOVLW 0x0
006C  20F4     ADDWFC PRODH, W, ACCESS
006E  6EDA     MOVWF FSR2H, ACCESS
0070  CFDE     MOVFF POSTINC2, __pcstackCOMRAM
0072  F001     NOP
0074  CFDD     MOVFF POSTDEC2, 0x2
0076  F002     NOP
0078  90D8     BCF STATUS, 0, ACCESS
007A  3601     RLCF __pcstackCOMRAM, F, ACCESS
007C  3602     RLCF 0x2, F, ACCESS
007E  C019     MOVFF i, 0x3
0080  F003     NOP
0082  C018     MOVFF data, 0x4
0084  F004     NOP
0086  2A03     INCF 0x3, F, ACCESS
0088  D002     BRA 0x8E
008A  90D8     BCF STATUS, 0, ACCESS
008C  3204     RRCF 0x4, F, ACCESS
008E  2E03     DECFSZ 0x3, F, ACCESS
0090  D7FC     BRA 0x8A
0092  0E01     MOVLW 0x1
0094  1604     ANDWF 0x4, F, ACCESS
0096  5004     MOVF 0x4, W, ACCESS
0098  1201     IORWF __pcstackCOMRAM, F, ACCESS
009A  0E00     MOVLW 0x0
009C  1202     IORWF 0x2, F, ACCESS
009E  5019     MOVF i, W, ACCESS
00A0  0D02     MULLW 0x2
00A2  0E25     MOVLW 0x25
00A4  24F3     ADDWF PROD, W, ACCESS
00A6  6ED9     MOVWF FSR2, ACCESS
00A8  0E00     MOVLW 0x0
00AA  20F4     ADDWFC PRODH, W, ACCESS
00AC  6EDA     MOVWF FSR2H, ACCESS
00AE  C001     MOVFF __pcstackCOMRAM, POSTINC2
00B0  FFDE     NOP
00B2  C002     MOVFF 0x2, POSTDEC2
00B4  FFDD     NOP
113:                   } while (i--);
00B6  0619     DECF i, F, ACCESS
00B8  2819     INCF i, W, ACCESS
00BA  A4D8     BTFSS STATUS, 2, ACCESS
00BC  D7D1     BRA 0x60
114:                   
115:                   data = PORTB;
00BE  CF81     MOVFF PORTB, data
00C0  F018     NOP
116:                   i = 7;
00C2  0E07     MOVLW 0x7
00C4  6E19     MOVWF i, ACCESS
117:                   do {
118:                       keypresses[i] = (keypresses[i] << 1) | ((data >> i) & 0x01);
00C6  5019     MOVF i, W, ACCESS
00C8  0D02     MULLW 0x2
00CA  0E25     MOVLW 0x25
00CC  24F3     ADDWF PROD, W, ACCESS
00CE  6ED9     MOVWF FSR2, ACCESS
00D0  0E00     MOVLW 0x0
00D2  20F4     ADDWFC PRODH, W, ACCESS
00D4  6EDA     MOVWF FSR2H, ACCESS
00D6  CFDE     MOVFF POSTINC2, __pcstackCOMRAM
00D8  F001     NOP
00DA  CFDD     MOVFF POSTDEC2, 0x2
00DC  F002     NOP
00DE  90D8     BCF STATUS, 0, ACCESS
00E0  3601     RLCF __pcstackCOMRAM, F, ACCESS
00E2  3602     RLCF 0x2, F, ACCESS
00E4  C019     MOVFF i, 0x3
00E6  F003     NOP
00E8  C018     MOVFF data, 0x4
00EA  F004     NOP
00EC  2A03     INCF 0x3, F, ACCESS
00EE  D002     BRA 0xF4
00F0  90D8     BCF STATUS, 0, ACCESS
00F2  3204     RRCF 0x4, F, ACCESS
00F4  2E03     DECFSZ 0x3, F, ACCESS
00F6  D7FC     BRA 0xF0
00F8  0E01     MOVLW 0x1
00FA  1604     ANDWF 0x4, F, ACCESS
00FC  5004     MOVF 0x4, W, ACCESS
00FE  1201     IORWF __pcstackCOMRAM, F, ACCESS
0100  0E00     MOVLW 0x0
0102  1202     IORWF 0x2, F, ACCESS
0104  5019     MOVF i, W, ACCESS
0106  0D02     MULLW 0x2
0108  0E25     MOVLW 0x25
010A  24F3     ADDWF PROD, W, ACCESS
010C  6ED9     MOVWF FSR2, ACCESS
010E  0E00     MOVLW 0x0
0110  20F4     ADDWFC PRODH, W, ACCESS
0112  6EDA     MOVWF FSR2H, ACCESS
0114  C001     MOVFF __pcstackCOMRAM, POSTINC2
0116  FFDE     NOP
0118  C002     MOVFF 0x2, POSTDEC2
011A  FFDD     NOP
119:                   } while (i-- - 8);
011C  0EF8     MOVLW 0xF8
011E  6E01     MOVWF __pcstackCOMRAM, ACCESS
0120  0EFF     MOVLW 0xFF
0122  6E02     MOVWF 0x2, ACCESS
0124  0619     DECF i, F, ACCESS
0126  2819     INCF i, W, ACCESS
0128  6E03     MOVWF 0x3, ACCESS
012A  6A04     CLRF 0x4, ACCESS
012C  5001     MOVF __pcstackCOMRAM, W, ACCESS
012E  2603     ADDWF 0x3, F, ACCESS
0130  5002     MOVF 0x2, W, ACCESS
0132  2204     ADDWFC 0x4, F, ACCESS
0134  5003     MOVF 0x3, W, ACCESS
0136  1004     IORWF 0x4, W, ACCESS
0138  A4D8     BTFSS STATUS, 2, ACCESS
013A  D7C5     BRA 0xC6
120:                   
121:                   // PORTB
122:                   // for (i = 8; i < NOTES; i++) {
123:                   //     keypresses[i] = (keypresses[i] << 1) | ((PORTB & (1 << i)) >> i);
124:                   // }
125:                   
126:                   // TODO same for PORTD when the steps board is printed
127:                   
128:                   // debug stuff
129:                   PORTDbits.RD4 = PORTAbits.RA0;
013C  A080     BTFSS PORTA, 0, ACCESS
013E  D002     BRA 0x144
0140  8883     BSF PORTD, 4, ACCESS
0142  D001     BRA 0x146
0144  9883     BCF PORTD, 4, ACCESS
130:                   PORTDbits.RD2 = (keypresses[0] && !(keypresses[0] & NOTE_MASK));
0146  0E00     MOVLW 0x0
0148  6E17     MOVWF 0x17, ACCESS
014A  5025     MOVF keypresses, W, ACCESS
014C  1026     IORWF 0x26, W, ACCESS
014E  B4D8     BTFSC STATUS, 2, ACCESS
0150  D006     BRA 0x15E
0152  0EFF     MOVLW 0xFF
0154  1426     ANDWF 0x26, W, ACCESS
0156  A4D8     BTFSS STATUS, 2, ACCESS
0158  D002     BRA 0x15E
015A  0E01     MOVLW 0x1
015C  6E17     MOVWF 0x17, ACCESS
015E  B017     BTFSC 0x17, 0, ACCESS
0160  D002     BRA 0x166
0162  9483     BCF PORTD, 2, ACCESS
0164  D001     BRA 0x168
0166  8483     BSF PORTD, 2, ACCESS
131:           
132:                   // reset interrupt flag
133:                   PIR1bits.TMR2IF = 0;
0168  929E     BCF PIR1, 1, ACCESS
134:               }
135:               
136:               PORTDbits.RD3 = 1;
016A  8683     BSF PORTD, 3, ACCESS
137:           }
016C  C016     MOVFF 0x16, 0x48
016E  F048     NOP
0170  C015     MOVFF 0x15, 0x47
0172  F047     NOP
0174  C014     MOVFF 0x14, 0x46
0176  F046     NOP
0178  C013     MOVFF 0x13, btemp
017A  F045     NOP
017C  C012     MOVFF 0x12, TABLAT
017E  FFF5     NOP
0180  C011     MOVFF 0x11, TBLPTRU
0182  FFF8     NOP
0184  C010     MOVFF 0x10, TBLPTRH
0186  FFF7     NOP
0188  C00F     MOVFF 0xF, TBLPTR
018A  FFF6     NOP
018C  C00E     MOVFF 0xE, PRODH
018E  FFF4     NOP
0190  C00D     MOVFF 0xD, PROD
0192  FFF3     NOP
0194  C00C     MOVFF 0xC, FSR2H
0196  FFDA     NOP
0198  C00B     MOVFF 0xB, FSR2
019A  FFD9     NOP
019C  C00A     MOVFF 0xA, FSR1H
019E  FFE2     NOP
01A0  C009     MOVFF 0x9, FSR1
01A2  FFE1     NOP
01A4  C008     MOVFF 0x8, FSR0H
01A6  FFEA     NOP
01A8  C007     MOVFF 0x7, FSR0
01AA  FFE9     NOP
01AC  C006     MOVFF 0x6, PCLATU
01AE  FFFB     NOP
01B0  C005     MOVFF 0x5, PCLATH
01B2  FFFA     NOP
01B4  9245     BCF btemp, 1, ACCESS
01B6  0011     RETFIE 1
138:           
139:           /* hardware configuration (inlined) */
140:           inline void init_hw(void)
141:           {
142:               di();
02A8  9EF2     BCF INTCON, 7, ACCESS
143:               
144:               /* PLL / FOSC configuration */
145:               // enable PLL
146:               OSCTUNEbits.PLLEN = 1;
02AA  8C9B     BSF OSCTUNE, 6, ACCESS
147:               // set FOSC to HFINTOSC (max frequency)
148:               OSCTUNEbits.TUN = 0b011111;
02AC  809B     BSF OSCTUNE, 0, ACCESS
02AE  829B     BSF OSCTUNE, 1, ACCESS
02B0  849B     BSF OSCTUNE, 2, ACCESS
02B2  869B     BSF OSCTUNE, 3, ACCESS
02B4  889B     BSF OSCTUNE, 4, ACCESS
02B6  9A9B     BCF OSCTUNE, 5, ACCESS
149:               // set 16 MHz oscillator, datasheet p.30
150:               OSCCONbits.IRCF = 0b111;
02B8  88D3     BSF OSCCON, 4, ACCESS
02BA  8AD3     BSF OSCCON, 5, ACCESS
02BC  8CD3     BSF OSCCON, 6, ACCESS
151:               // select primary clock (with PLL)
152:               OSCCONbits.SCS = 0b00;
02BE  0EFC     MOVLW 0xFC
02C0  16D3     ANDWF OSCCON, F, ACCESS
153:               
154:               /* i/o initializazion */
155:               // disable all ADCs
156:               ANSELA = 0x00;
02C2  0E00     MOVLW 0x0
02C4  010F     MOVLB 0xF
02C6  6F38     MOVWF 0x38, BANKED
157:               ANSELB = 0x00;
02C8  0E00     MOVLW 0x0
02CA  6F39     MOVWF 0x39, BANKED
158:               ANSELC = 0x00;
02CC  0E00     MOVLW 0x0
02CE  6F3A     MOVWF 0x3A, BANKED
159:               ANSELD = 0x00;
02D0  0E00     MOVLW 0x0
02D2  6F3B     MOVWF 0x3B, BANKED
160:           
161:               // TODO: remove demo
162:               TRISA = 0xFF;
02D4  6892     SETF TRISA, ACCESS
163:               TRISB = 0xFF;
02D6  6893     SETF TRISB, ACCESS
164:               
165:               TRISDbits.TRISD1 = 0;
02D8  9295     BCF TRISD, 1, ACCESS
166:               TRISDbits.TRISD2 = 0;
02DA  9495     BCF TRISD, 2, ACCESS
167:               TRISDbits.TRISD3 = 0;
02DC  9695     BCF TRISD, 3, ACCESS
168:               TRISDbits.TRISD4 = 0;
02DE  9895     BCF TRISD, 4, ACCESS
169:               
170:               // LED
171:               PORTDbits.RD1 = 1;
02E0  8283     BSF PORTD, 1, ACCESS
172:               // TEST OUTPUT 1
173:               PORTDbits.RD2 = 0;
02E2  9483     BCF PORTD, 2, ACCESS
174:               // TEST OUTPUT 2
175:               PORTDbits.RD3 = 1;
02E4  8683     BSF PORTD, 3, ACCESS
176:               // TEST OUTPUT 3
177:               PORTDbits.RD4 = 0;
02E6  9883     BCF PORTD, 4, ACCESS
178:           
179:               /* timer configuration */
180:               // timer 2 comp value
181:               PR2 = 128;
02E8  0E80     MOVLW 0x80
02EA  6EBB     MOVWF PR2, ACCESS
182:               // postscaler 1:4
183:               T2CONbits.T2OUTPS = 0b0011;
02EC  50BA     MOVF T2CON, W, ACCESS
02EE  0B87     ANDLW 0x87
02F0  0918     IORLW 0x18
02F2  6EBA     MOVWF T2CON, ACCESS
184:               // prescaler 1:16
185:               T2CONbits.T2CKPS = 0b11;
02F4  0E03     MOVLW 0x3
02F6  12BA     IORWF T2CON, F, ACCESS
186:               // start timer
187:               T2CONbits.TMR2ON = 1;
02F8  84BA     BSF T2CON, 2, ACCESS
188:               
189:               // timer 2 interrupts
190:               PIE1bits.TMR2IE = 1;
02FA  829D     BSF PIE1, 1, ACCESS
191:               PIR1bits.TMR2IF = 0;
02FC  929E     BCF PIR1, 1, ACCESS
192:           
193:               // enable peripheral interrupts
194:               INTCONbits.PEIE = 1;
02FE  8CF2     BSF INTCON, 6, ACCESS
195:               
196:               /* serial configuration */
197:               eusart1_init();
0300  ECFE     CALL 0x3FC, 0
0302  F001     NOP
198:           
199:               ei();
0304  8EF2     BSF INTCON, 7, ACCESS
200:           }
0306  0012     RETURN 0
201:           
202:           
203:           /* main program */
204:           void main(void)
205:           {
206:               unsigned char i, data;
207:               midi_message_t sample_message;
208:               
209:               /* setup hardware */
210:               init_hw();
0308  EC54     CALL 0x2A8, 0
030A  F001     NOP
211:              
212:               /* setup software */
213:               memset(keypresses, 0, sizeof(keypresses));
030C  0E25     MOVLW 0x25
030E  6E1A     MOVWF p1, ACCESS
0310  0E00     MOVLW 0x0
0312  6E1B     MOVWF pkt, ACCESS
0314  0E00     MOVLW 0x0
0316  6E1D     MOVWF 0x1D, ACCESS
0318  0E00     MOVLW 0x0
031A  6E1C     MOVWF c, ACCESS
031C  0E00     MOVLW 0x0
031E  6E1F     MOVWF pkt, ACCESS
0320  0E1E     MOVLW 0x1E
0322  6E1E     MOVWF n, ACCESS
0324  ECC3     CALL 0x386, 0
0326  F001     NOP
214:               
215:               /* TODO remove demo code */
216:               midi_note_on(&sample_message, 0x0, 0x3C, 0x7F); 
0328  0E62     MOVLW 0x62
032A  6E1F     MOVWF pkt, ACCESS
032C  0E00     MOVLW 0x0
032E  6E20     MOVWF p, ACCESS
0330  0E00     MOVLW 0x0
0332  6E22     MOVWF 0x22, ACCESS
0334  0E00     MOVLW 0x0
0336  6E21     MOVWF channel, ACCESS
0338  0E3C     MOVLW 0x3C
033A  6E23     MOVWF note, ACCESS
033C  0E7F     MOVLW 0x7F
033E  6E24     MOVWF velocity, ACCESS
0340  ECDE     CALL 0x1BC, 0
0342  F000     NOP
217:               PORTDbits.RD1 = 0;
0344  9283     BCF PORTD, 1, ACCESS
218:               
219:               /* main loop */
220:               while (1) {
0352  D7F9     BRA 0x346
221:                   eusart_write_midi(&sample_message);
0346  0E62     MOVLW 0x62
0348  6E1B     MOVWF pkt, ACCESS
034A  0E00     MOVLW 0x0
034C  6E1C     MOVWF c, ACCESS
034E  EC1A     CALL 0x234, 0
0350  F001     NOP
0352  D7F9     BRA 0x346
222:               }
223:           }
224:           
225:           
226:           int eusart_write_midi(const midi_message_t *pkt)
227:           {
228:               size_t length;
229:               uint8_t *data;
230:               
231:               if (pkt == NULL) {
0234  501B     MOVF pkt, W, ACCESS
0236  101C     IORWF c, W, ACCESS
0238  B4D8     BTFSC STATUS, 2, ACCESS
023A  0012     RETURN 0
232:                   return -1;
233:               }
234:               
235:               length = pkt->data_size;
023C  EE20     LFSR 2, 0x1
023E  F001     NOP
0240  501B     MOVF pkt, W, ACCESS
0242  26D9     ADDWF FSR2, F, ACCESS
0244  501C     MOVF c, W, ACCESS
0246  22DA     ADDWFC FSR2H, F, ACCESS
0248  CFDE     MOVFF POSTINC2, pkt
024A  F01F     NOP
024C  CFDD     MOVFF POSTDEC2, p
024E  F020     NOP
236:               data = (uint8_t *) pkt->data;
0250  0E03     MOVLW 0x3
0252  241B     ADDWF pkt, W, ACCESS
0254  6E21     MOVWF channel, ACCESS
0256  0E00     MOVLW 0x0
0258  201C     ADDWFC c, W, ACCESS
025A  6E22     MOVWF 0x22, ACCESS
237:               
238:               putch((char)((pkt->status << 4) | pkt->channel));
025C  C01B     MOVFF pkt, FSR2
025E  FFD9     NOP
0260  C01C     MOVFF c, FSR2H
0262  FFDA     NOP
0264  38DF     SWAPF INDF2, W, ACCESS
0266  0B0F     ANDLW 0xF
0268  6E1D     MOVWF 0x1D, ACCESS
026A  C01B     MOVFF pkt, FSR2
026C  FFD9     NOP
026E  C01C     MOVFF c, FSR2H
0270  FFDA     NOP
0272  50DF     MOVF INDF2, W, ACCESS
0274  0B0F     ANDLW 0xF
0276  6E1E     MOVWF n, ACCESS
0278  381E     SWAPF n, W, ACCESS
027A  0BF0     ANDLW 0xF0
027C  101D     IORWF 0x1D, W, ACCESS
027E  EC0C     CALL 0x418, 0
0280  F002     NOP
239:               
240:               while (length--) {
0282  D009     BRA 0x296
241:                   putch((char) *(data++));
0284  C021     MOVFF channel, FSR2
0286  FFD9     NOP
0288  C022     MOVFF 0x22, FSR2H
028A  FFDA     NOP
028C  50DF     MOVF INDF2, W, ACCESS
028E  EC0C     CALL 0x418, 0
0290  F002     NOP
0292  4A21     INFSNZ channel, F, ACCESS
0294  2A22     INCF 0x22, F, ACCESS
242:               }
0296  061F     DECF pkt, F, ACCESS
0298  A0D8     BTFSS STATUS, 0, ACCESS
029A  0620     DECF p, F, ACCESS
029C  281F     INCF pkt, W, ACCESS
029E  E1F2     BNZ 0x284
02A0  2820     INCF p, W, ACCESS
02A2  B4D8     BTFSC STATUS, 2, ACCESS
02A4  0012     RETURN 0
02A6  D7EE     BRA 0x284
243:               
244:               return 0;
245:           }
---  C:/Program Files/Microchip/xc8/v1.44/sources/common/memset.c  --------------------------------------
1:             #include	<string.h>
2:             
3:             #ifdef _PIC16
4:             far void *
5:             memset(far void * p1, int c, register size_t n)
6:             #else /*  _PIC16 */
7:             void *
8:             memset(void * p1, int c, register size_t n)
9:             #endif /* _PIC16 */
10:            {
11:            
12:            #ifdef _PIC16
13:            	register far char *	p;
14:            #else /*  _PIC16 */
15:            	register char *		p;
16:            #endif /* _PIC16 */
17:            
18:            	p = p1;
0386  C01A     MOVFF p1, p
0388  F020     NOP
038A  C01B     MOVFF pkt, channel
038C  F021     NOP
19:            	while(n--)
038E  D008     BRA 0x3A0
03A0  061E     DECF n, F, ACCESS
20:            		*p++ = c;
0390  C020     MOVFF p, FSR2
0392  FFD9     NOP
0394  C021     MOVFF channel, FSR2H
0396  FFDA     NOP
0398  C01C     MOVFF c, INDF2
039A  FFDF     NOP
039C  4A20     INFSNZ p, F, ACCESS
039E  2A21     INCF channel, F, ACCESS
03A0  061E     DECF n, F, ACCESS
03A2  A0D8     BTFSS STATUS, 0, ACCESS
03A4  061F     DECF pkt, F, ACCESS
03A6  281E     INCF n, W, ACCESS
03A8  E1F3     BNZ 0x390
03AA  281F     INCF pkt, W, ACCESS
03AC  B4D8     BTFSC STATUS, 2, ACCESS
03AE  0012     RETURN 0
03B0  D7EF     BRA 0x390
21:            	return p1;
22:            }