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authorNao Pross <naopross@thearcway.org>2017-05-18 15:50:51 +0200
committerNao Pross <naopross@thearcway.org>2017-05-18 15:50:51 +0200
commit7cf70014c1edf75c7e2b26eba24b0a02ced853f4 (patch)
treeff6c4e055195ed57cafd36f9071f155473eb4d33 /hw/Project Logs for z80uPC/MainSheet SCH ECO 20.03.2017 08-17-19.LOG
parentwiring for P4 and P5 (I/O ports) and circuits for CLKs and RST (diff)
downloadz80uPC-7cf70014c1edf75c7e2b26eba24b0a02ced853f4.tar.gz
z80uPC-7cf70014c1edf75c7e2b26eba24b0a02ced853f4.zip
wiring for CTC (U8) to address bus and data bus
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