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| author | Nao Pross <naopross@thearcway.org> | 2017-05-23 11:51:48 +0200 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-05-23 11:51:48 +0200 |
| commit | a29b4fd588d6f3136bfef0d5dc1ee40ead328b15 (patch) | |
| tree | a39f231b7025c754c9ee643dde6efd416db269ee /hw/Project Outputs for z80uPC/Status Report.Txt | |
| parent | finish wiring and add eurocard compliant standard holes (diff) | |
| download | z80uPC-a29b4fd588d6f3136bfef0d5dc1ee40ead328b15.tar.gz z80uPC-a29b4fd588d6f3136bfef0d5dc1ee40ead328b15.zip | |
board complete, generate gerber (x2) fileshardware
this is probably the last commit before printing the PCB, unless there are some
other errors in the board design
Diffstat (limited to 'hw/Project Outputs for z80uPC/Status Report.Txt')
| -rw-r--r-- | hw/Project Outputs for z80uPC/Status Report.Txt | 36 |
1 files changed, 30 insertions, 6 deletions
diff --git a/hw/Project Outputs for z80uPC/Status Report.Txt b/hw/Project Outputs for z80uPC/Status Report.Txt index 6b5e7df..3cf8803 100644 --- a/hw/Project Outputs for z80uPC/Status Report.Txt +++ b/hw/Project Outputs for z80uPC/Status Report.Txt @@ -1,10 +1,34 @@ -Output: Protel -Type : ProtelNetlist -From : Project [z80uPC.PrjPCB] - Generated File[MainSheet.NET] +Project Outputs Generation Report +--------------------------------- +Start Output Generation At 09:54:31 On 23.05.2017 +Output: Gerber X2 Files +Type : GerberX2 +From : PCB Document [MainBoard.PcbDoc] + Generated File[MainBoard_Copper_Signal_Top.gbr] + Generated File[MainBoard_Copper_Plane_1.gbr] + Generated File[MainBoard_Copper_Plane_2.gbr] + Generated File[MainBoard_Copper_Signal_Bot.gbr] + Generated File[MainBoard_Pads_Bot.gbr] + Generated File[MainBoard_Pads_Top.gbr] + Generated File[MainBoard_Legend_Top.gbr] + Generated File[MainBoard_Soldermask_Top.gbr] + Generated File[MainBoard_Paste_Bot.gbr] + Generated File[MainBoard_Legend_Bot.gbr] + Generated File[MainBoard_Soldermask_Bot.gbr] + Generated File[MainBoard_Paste_Top.gbr] + Generated File[MainBoard_Mechanical_15.gbr] + Generated File[MainBoard_Profile.gbr] + Generated File[MainBoard_NPTH_Drill.gbr] + Generated File[MainBoard_PTH_Drill.gbr] + Generated File[MainBoard_Drawing_1.gbr] + Generated File[MainBoard_Drillmap_1.gbr] + Generated File[MainBoard.RUL] + Generated File[MainBoard.EXTREP] + Generated File[MainBoard.REP] -Files Generated : 1 + +Files Generated : 21 Documents Printed : 0 -Finished Output Generation At 10:54:34 On 06.03.2017 +Finished Output Generation At 09:54:33 On 23.05.2017 |