switch from GAL (pld) to M4 32/32 CPLD

add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port

1 files changed, 37 insertions, 0 deletions

diff --git a/sw/cpld/address_decoder.vhd b/sw/cpld/address_decoder.vhd
new file mode 100644
index 0000000..2c80f86
--- /dev/null
+++ b/sw/cpld/address_decoder.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity ADDRESS_DECODER is
+
+port(
+	-- address input
+	PA: in unsigned(15 downto 0);
+
+	-- chip selects output
+	-- memory
+	CSROMH: out std_logic;
+	CSROML: out std_logic;
+	CSRAM : out std_logic;
+	-- io chips
+	CSUART: out std_logic;
+	CSCTC : out std_logic;
+	CSPIO : out std_logic
+);
+
+end;
+
+architecture Behavioral of ADDRESS_DECODER is
+begin
+	-- memory
+	CSROMH <= 0 when ((PA >= x"0000") and (PA < x"2000"));
+	CSROML <= 0 when ((PA >= x"4000") and (PA < x"4000"));
+	CSRAM  <= 0 when (PA >= x"D000");
+	-- io chips
+	CSUART <= 0 when ((PA >= x"4000") and (PA < x"4008"));
+	-- CSCTC
+	-- CSPIO 
+
+end Behavioral;
+