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authorNao Pross <naopross@thearcway.org>2017-06-16 15:25:54 +0200
committerNao Pross <naopross@thearcway.org>2017-06-16 15:25:54 +0200
commit6105426e159a55cfb15fee3e999bb4fcf6289446 (patch)
tree658b62ff706fcd81674901bc4bfd4dbb9667ebdd /sw/cpld_test/cpld_test.STY
parentfixed typo in usart.h and in doc (diff)
downloadz80uPC-6105426e159a55cfb15fee3e999bb4fcf6289446.tar.gz
z80uPC-6105426e159a55cfb15fee3e999bb4fcf6289446.zip
new components list and cpld test unit
Diffstat (limited to '')
-rw-r--r--sw/cpld_test/cpld_test.STY22
1 files changed, 22 insertions, 0 deletions
diff --git a/sw/cpld_test/cpld_test.STY b/sw/cpld_test/cpld_test.STY
new file mode 100644
index 0000000..3b3c6ba
--- /dev/null
+++ b/sw/cpld_test/cpld_test.STY
@@ -0,0 +1,22 @@
+[Normal]
+synlibXRef=lc4k_pvhd, VHDL.TASKLSVhd, 0, Yes
+_EdfFrequency=lc4k_pvhd, VHDL.TASKLSVhd, 0, 200
+_EdfInConsFile=lc4k_pvhd, VHDL.TASKLSVhd, 0,
+_EdfSymFSM=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfFanin=lc4k_pvhd, VHDL.TASKLSVhd, 0, 20
+_EdfMaxMacrocell=lc4k_pvhd, VHDL.TASKLSVhd, 0, 16
+_EdfPerDesignOptTiming=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0
+_EdfOutputPreFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfMapLogic=lc4k_pvhd, VHDL.TASKLSVhd, 0, False
+_EdfInsertIO=lc4k_pvhd, VHDL.TASKLSVhd, 0, False
+_EdfOutNetForm=lc4k_pvhd, VHDL.TASKLSVhd, 0, None
+_EdfNumCritPath=lc4k_pvhd, VHDL.TASKLSVhd, 0, 3
+_EdfUnconsClk=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfNumStartEnd=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0
+_EdfResSharing=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfPushTirstates=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfDefEnumEncode=lc4k_pvhd, VHDL.TASKLSVhd, 0, default
+_EdfArrangeVHDLFiles=lc4k_pvhd, VHDL.TASKLSVhd, 0, True
+_EdfSynOnOffImp=lc4k_pvhd, VHDL.TASKLSVhd, 0, False
+[STRATEGY-LIST]
+Normal=True, 1496317751