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| author | Nao Pross <naopross@thearcway.org> | 2017-11-23 14:34:55 +0100 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-11-23 14:34:55 +0100 |
| commit | 141137dfe5bdc7400d5cc1ad388b670f9f2e9446 (patch) | |
| tree | bef58de3c44787dadb22ec9cf452a3606ddd6708 /sw/cpld_test/cpld_test.lct.bak | |
| parent | Improvements in PIO driver, pio test rewritten in inline asm (diff) | |
| download | z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.tar.gz z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.zip | |
update cpld files from VHDL dev machine and delete programmer code (unused)
Diffstat (limited to 'sw/cpld_test/cpld_test.lct.bak')
| -rw-r--r-- | sw/cpld_test/cpld_test.lct.bak | 113 |
1 files changed, 0 insertions, 113 deletions
diff --git a/sw/cpld_test/cpld_test.lct.bak b/sw/cpld_test/cpld_test.lct.bak deleted file mode 100644 index 4bdf950..0000000 --- a/sw/cpld_test/cpld_test.lct.bak +++ /dev/null @@ -1,113 +0,0 @@ - -[Device] -Family = lc4k; -PartNumber = LC4064ZE-5UMN64C; -Package = 64ucBGA; -PartType = LC4064ZE; -Speed = -5.8; -Operating_condition = COM; -Status = Production; - -[Revision] -Parent = lc4k64e.lci; -DATE = 2002; -TIME = 0:00:00; -Source_Format = Pure_VHDL; -Synthesis = Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -layer = OFF; - -[Group Assignments] -layer = OFF; - -[Resource Reservations] -layer = OFF; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] -NetList = VHDL; - -[IO Types] -layer = OFF; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - -[opt global constraints list] - -[Explorer User Settings] - -[Pin attributes list] - -[global constraints list] - -[Global Constraints Process Update] - -[pin lock limitation] - -[LOCATION ASSIGNMENTS LIST] - -[RESOURCE RESERVATIONS LIST] - -[individual constraints list] - -[Attributes list setting] - -[Timing Analyzer] - -[PLL Assignments] - -[Dual Function Macrocell] - -[Explorer Results] - -[VHDL synplify constraints] - -[VHDL spectrum constraints] - -[verilog synplify constraints] - -[verilog spectrum constraints] - -[VHDL synplify constraints list] - -[VHDL spectrum constraints list] - -[verilog synplify constraints list] - -[verilog spectrum constraints list] - -[Power Guard] - -[ORP Bypass] - -[Register Powerup] |