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| author | Nao Pross <naopross@thearcway.org> | 2017-06-16 15:25:54 +0200 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-06-16 15:25:54 +0200 |
| commit | 6105426e159a55cfb15fee3e999bb4fcf6289446 (patch) | |
| tree | 658b62ff706fcd81674901bc4bfd4dbb9667ebdd /sw/cpld_test/cpld_test.syn | |
| parent | fixed typo in usart.h and in doc (diff) | |
| download | z80uPC-6105426e159a55cfb15fee3e999bb4fcf6289446.tar.gz z80uPC-6105426e159a55cfb15fee3e999bb4fcf6289446.zip | |
new components list and cpld test unit
Diffstat (limited to '')
| -rw-r--r-- | sw/cpld_test/cpld_test.syn | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sw/cpld_test/cpld_test.syn b/sw/cpld_test/cpld_test.syn new file mode 100644 index 0000000..06b6554 --- /dev/null +++ b/sw/cpld_test/cpld_test.syn @@ -0,0 +1,11 @@ +JDF B +// Created by Version 2.0 +PROJECT cpld_test +DESIGN cpld_test Normal +DEVKIT M4A5-32/32-10JC +ENTRY Pure VHDL +MODULE cpld_test.vhd +MODSTYLE cpld_test Normal +SYNTHESIS_TOOL Synplify +SIMULATOR_TOOL ActiveHDL +TOPMODULE cpld_test |