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authorNao Pross <naopross@thearcway.org>2017-11-23 14:34:55 +0100
committerNao Pross <naopross@thearcway.org>2017-11-23 14:34:55 +0100
commit141137dfe5bdc7400d5cc1ad388b670f9f2e9446 (patch)
treebef58de3c44787dadb22ec9cf452a3606ddd6708 /sw/cpld_test/cpld_test.vhd
parentImprovements in PIO driver, pio test rewritten in inline asm (diff)
downloadz80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.tar.gz
z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.zip
update cpld files from VHDL dev machine and delete programmer code (unused)
Diffstat (limited to 'sw/cpld_test/cpld_test.vhd')
-rw-r--r--sw/cpld_test/cpld_test.vhd15
1 files changed, 0 insertions, 15 deletions
diff --git a/sw/cpld_test/cpld_test.vhd b/sw/cpld_test/cpld_test.vhd
deleted file mode 100644
index b1161e9..0000000
--- a/sw/cpld_test/cpld_test.vhd
+++ /dev/null
@@ -1,15 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-entity cpld_test is
- IN_PIN: in std_logic;
- OUT_PIN: out std_logic;
-end;
-
-architecture behavioral of cpld_test is
-begin
- OUT_PIN <= not(IN_PIN);
-end behavioral;
-