update cpld files from VHDL dev machine and delete programmer code (unused)

1 files changed, 0 insertions, 54 deletions

diff --git a/sw/cpld_test/scratchproject.prs b/sw/cpld_test/scratchproject.prs
deleted file mode 100644
index 9db3bb5..0000000
--- a/sw/cpld_test/scratchproject.prs
+++ /dev/null
@@ -1,54 +0,0 @@
-#--  Synopsys, Inc.
-#--  Version I-2014.03LC 
-#--  Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\scratchproject.prs
-
-#project files
-add_file -vhdl -lib work "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.vhd"
-
-
-
-#implementation: "cpld_test"
-impl -add \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test -type fpga
-
-#device options
-set_option -technology mach
-set_option -part M4A5-32
-set_option -package ""
-set_option -speed_grade ""
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "cpld_test"
-
-# mapper_options
-set_option -frequency 1
-set_option -write_verilog 0
-set_option -write_vhdl 0
-set_option -srs_instrumentation 1
-
-# Lattice ispMACH4000
-set_option -maxfanin 20
-set_option -RWCheckOnRam 1
-set_option -maxterms 16
-set_option -areadelay 0
-set_option -disable_io_insertion 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi"
-
-#set log file 
-set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" 
-impl -active "cpld_test"