diff options
| -rw-r--r-- | hw/History/z80uPC.~(1).PrjPCB.Zip | bin | 0 -> 4389 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(1).SchLib.Zip | bin | 0 -> 1139 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(2).SchLib.Zip | bin | 0 -> 1175 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(3).SchLib.Zip | bin | 0 -> 1509 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(4).SchLib.Zip | bin | 0 -> 1832 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(5).SchLib.Zip | bin | 0 -> 1843 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(6).SchLib.Zip | bin | 0 -> 1883 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(7).SchLib.Zip | bin | 0 -> 2212 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(8).SchLib.Zip | bin | 0 -> 2377 bytes | |||
| -rw-r--r-- | hw/History/zilog_z80.~(9).SchLib.Zip | bin | 0 -> 2378 bytes | |||
| -rw-r--r-- | hw/z80uPC.PrjPCB | 1005 | ||||
| -rw-r--r-- | hw/zilog_z80.SchLib | bin | 0 -> 12288 bytes |
12 files changed, 1005 insertions, 0 deletions
diff --git a/hw/History/z80uPC.~(1).PrjPCB.Zip b/hw/History/z80uPC.~(1).PrjPCB.Zip Binary files differnew file mode 100644 index 0000000..82d4bfe --- /dev/null +++ b/hw/History/z80uPC.~(1).PrjPCB.Zip diff --git a/hw/History/zilog_z80.~(1).SchLib.Zip b/hw/History/zilog_z80.~(1).SchLib.Zip Binary files differnew file mode 100644 index 0000000..5dc3c80 --- /dev/null +++ b/hw/History/zilog_z80.~(1).SchLib.Zip diff --git a/hw/History/zilog_z80.~(2).SchLib.Zip b/hw/History/zilog_z80.~(2).SchLib.Zip Binary files differnew file mode 100644 index 0000000..ebe1658 --- /dev/null +++ b/hw/History/zilog_z80.~(2).SchLib.Zip diff --git a/hw/History/zilog_z80.~(3).SchLib.Zip b/hw/History/zilog_z80.~(3).SchLib.Zip Binary files differnew file mode 100644 index 0000000..e821df8 --- /dev/null +++ b/hw/History/zilog_z80.~(3).SchLib.Zip diff --git a/hw/History/zilog_z80.~(4).SchLib.Zip b/hw/History/zilog_z80.~(4).SchLib.Zip Binary files differnew file mode 100644 index 0000000..e2e7057 --- /dev/null +++ b/hw/History/zilog_z80.~(4).SchLib.Zip diff --git a/hw/History/zilog_z80.~(5).SchLib.Zip b/hw/History/zilog_z80.~(5).SchLib.Zip Binary files differnew file mode 100644 index 0000000..95de165 --- /dev/null +++ b/hw/History/zilog_z80.~(5).SchLib.Zip diff --git a/hw/History/zilog_z80.~(6).SchLib.Zip b/hw/History/zilog_z80.~(6).SchLib.Zip Binary files differnew file mode 100644 index 0000000..e5e23a6 --- /dev/null +++ b/hw/History/zilog_z80.~(6).SchLib.Zip diff --git a/hw/History/zilog_z80.~(7).SchLib.Zip b/hw/History/zilog_z80.~(7).SchLib.Zip Binary files differnew file mode 100644 index 0000000..5f09f4d --- /dev/null +++ b/hw/History/zilog_z80.~(7).SchLib.Zip diff --git a/hw/History/zilog_z80.~(8).SchLib.Zip b/hw/History/zilog_z80.~(8).SchLib.Zip Binary files differnew file mode 100644 index 0000000..3cc62e9 --- /dev/null +++ b/hw/History/zilog_z80.~(8).SchLib.Zip diff --git a/hw/History/zilog_z80.~(9).SchLib.Zip b/hw/History/zilog_z80.~(9).SchLib.Zip Binary files differnew file mode 100644 index 0000000..d28fab5 --- /dev/null +++ b/hw/History/zilog_z80.~(9).SchLib.Zip diff --git a/hw/z80uPC.PrjPCB b/hw/z80uPC.PrjPCB new file mode 100644 index 0000000..d7834c8 --- /dev/null +++ b/hw/z80uPC.PrjPCB @@ -0,0 +1,1005 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ReleaseVaultGUID= +ReleaseVaultName= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Default Configuration +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=zilog_z80.SchLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=SBNDOXLC + +[Configuration1] +Name=Default Configuration +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +CurrentRevision= +Variant=[No Variations] +OutputJobsCount=0 + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=\\SRV004\PR805001 - SHARP MX-4141N +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=Verilog +OutputName20=Verilog File +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 +OutputType21=VHDL +OutputName21=VHDL File +OutputDocumentPath21= +OutputVariantName21= +OutputDefault21=0 +OutputType22=WireListNetlist +OutputName22=WireList Netlist +OutputDocumentPath22= +OutputVariantName22= +OutputDefault22=0 +OutputType23=XSpiceNetlist +OutputName23=XSpice Netlist +OutputDocumentPath23= +OutputVariantName23= +OutputDefault23=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=\\SRV004\PR805001 - SHARP MX-4141N +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AdvSimNetlist +OutputName1=Mixed Sim +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=\\SRV004\PR805001 - SHARP MX-4141N +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembler Source Print +OutputName1=Assembler Source Prints +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType2=C Source Print +OutputName2=C Source Prints +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=C/C++ Header Print +OutputName3=C/C++ Header Prints +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=C++ Source Print +OutputName4=C++ Source Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Composite +OutputName5=Composite Drawing +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType6=FSM Print +OutputName6=FSM Prints +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType7=OpenBus Print +OutputName7=OpenBus Prints +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType8=PCB 3D Print +OutputName8=PCB 3D Print +OutputDocumentPath8= +OutputVariantName8=[No Variations] +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=PCB 3D Video +OutputName9=PCB 3D Video +OutputDocumentPath9= +OutputVariantName9=[No Variations] +OutputDefault9=0 +PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType10=PCB Print +OutputName10=PCB Prints +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 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+OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType9=NC Drill +OutputName9=NC Drill Files +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=ODB +OutputName10=ODB++ Files +OutputDocumentPath10= +OutputVariantName10=[No Variations] +OutputDefault10=0 +OutputType11=Plane +OutputName11=Power-Plane Prints +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType12=Test Points +OutputName12=Test Point Report +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 + +[OutputGroup6] +Name=Report Outputs +Description= +TargetPrinter=\\SRV004\PR805001 - SHARP MX-4141N +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_PartType +OutputName1=Bill of Materials +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 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+Description= +TargetPrinter=\\SRV004\PR805001 - SHARP MX-4141N +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportSTEP +OutputName4=Export STEP +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=NetList Sch +OutputName5=NetList Sch +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 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