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-rw-r--r--sw/z80/drivers/build/ctc.asm52
-rw-r--r--sw/z80/drivers/build/ctc.lst52
-rw-r--r--sw/z80/drivers/build/ctc.rel19
-rw-r--r--sw/z80/drivers/build/ctc.sym27
-rw-r--r--sw/z80/drivers/build/pio.asm234
-rw-r--r--sw/z80/drivers/build/pio.lst234
-rw-r--r--sw/z80/drivers/build/pio.rel87
-rw-r--r--sw/z80/drivers/build/pio.sym36
-rw-r--r--sw/z80/drivers/build/usart.asm440
-rw-r--r--sw/z80/drivers/build/usart.lst440
-rw-r--r--sw/z80/drivers/build/usart.rel184
-rw-r--r--sw/z80/drivers/build/usart.sym38
12 files changed, 1843 insertions, 0 deletions
diff --git a/sw/z80/drivers/build/ctc.asm b/sw/z80/drivers/build/ctc.asm
new file mode 100644
index 0000000..838756a
--- /dev/null
+++ b/sw/z80/drivers/build/ctc.asm
@@ -0,0 +1,52 @@
+;--------------------------------------------------------
+; File Created by SDCC : free open source ANSI-C Compiler
+; Version 3.6.0 #9615 (Linux)
+;--------------------------------------------------------
+ .module ctc
+ .optsdcc -mz80
+
+;--------------------------------------------------------
+; Public variables in this module
+;--------------------------------------------------------
+ .globl _ctc_control
+;--------------------------------------------------------
+; special function registers
+;--------------------------------------------------------
+;--------------------------------------------------------
+; ram data
+;--------------------------------------------------------
+ .area _DATA
+;--------------------------------------------------------
+; ram data
+;--------------------------------------------------------
+ .area _INITIALIZED
+;--------------------------------------------------------
+; absolute external ram data
+;--------------------------------------------------------
+ .area _DABS (ABS)
+;--------------------------------------------------------
+; global & static initialisations
+;--------------------------------------------------------
+ .area _HOME
+ .area _GSINIT
+ .area _GSFINAL
+ .area _GSINIT
+;--------------------------------------------------------
+; Home
+;--------------------------------------------------------
+ .area _HOME
+ .area _HOME
+;--------------------------------------------------------
+; code
+;--------------------------------------------------------
+ .area _CODE
+;ctc.c:3: void ctc_control()
+; ---------------------------------
+; Function ctc_control
+; ---------------------------------
+_ctc_control::
+;ctc.c:6: }
+ ret
+ .area _CODE
+ .area _INITIALIZER
+ .area _CABS (ABS)
diff --git a/sw/z80/drivers/build/ctc.lst b/sw/z80/drivers/build/ctc.lst
new file mode 100644
index 0000000..e758d8a
--- /dev/null
+++ b/sw/z80/drivers/build/ctc.lst
@@ -0,0 +1,52 @@
+ 1 ;--------------------------------------------------------
+ 2 ; File Created by SDCC : free open source ANSI-C Compiler
+ 3 ; Version 3.6.0 #9615 (Linux)
+ 4 ;--------------------------------------------------------
+ 5 .module ctc
+ 6 .optsdcc -mz80
+ 7
+ 8 ;--------------------------------------------------------
+ 9 ; Public variables in this module
+ 10 ;--------------------------------------------------------
+ 11 .globl _ctc_control
+ 12 ;--------------------------------------------------------
+ 13 ; special function registers
+ 14 ;--------------------------------------------------------
+ 15 ;--------------------------------------------------------
+ 16 ; ram data
+ 17 ;--------------------------------------------------------
+ 18 .area _DATA
+ 19 ;--------------------------------------------------------
+ 20 ; ram data
+ 21 ;--------------------------------------------------------
+ 22 .area _INITIALIZED
+ 23 ;--------------------------------------------------------
+ 24 ; absolute external ram data
+ 25 ;--------------------------------------------------------
+ 26 .area _DABS (ABS)
+ 27 ;--------------------------------------------------------
+ 28 ; global & static initialisations
+ 29 ;--------------------------------------------------------
+ 30 .area _HOME
+ 31 .area _GSINIT
+ 32 .area _GSFINAL
+ 33 .area _GSINIT
+ 34 ;--------------------------------------------------------
+ 35 ; Home
+ 36 ;--------------------------------------------------------
+ 37 .area _HOME
+ 38 .area _HOME
+ 39 ;--------------------------------------------------------
+ 40 ; code
+ 41 ;--------------------------------------------------------
+ 42 .area _CODE
+ 43 ;ctc.c:3: void ctc_control()
+ 44 ; ---------------------------------
+ 45 ; Function ctc_control
+ 46 ; ---------------------------------
+ 0000 47 _ctc_control::
+ 48 ;ctc.c:6: }
+ 0000 C9 [10] 49 ret
+ 50 .area _CODE
+ 51 .area _INITIALIZER
+ 52 .area _CABS (ABS)
diff --git a/sw/z80/drivers/build/ctc.rel b/sw/z80/drivers/build/ctc.rel
new file mode 100644
index 0000000..50a8b42
--- /dev/null
+++ b/sw/z80/drivers/build/ctc.rel
@@ -0,0 +1,19 @@
+XL2
+H 9 areas 2 global symbols
+M ctc
+O -mz80
+S .__.ABS. Def0000
+A _CODE size 1 flags 0 addr 0
+S _ctc_control Def0000
+A _DATA size 0 flags 0 addr 0
+A _INITIALIZED size 0 flags 0 addr 0
+A _DABS size 0 flags 8 addr 0
+A _HOME size 0 flags 0 addr 0
+A _GSINIT size 0 flags 0 addr 0
+A _GSFINAL size 0 flags 0 addr 0
+A _INITIALIZER size 0 flags 0 addr 0
+A _CABS size 0 flags 8 addr 0
+T 00 00
+R 00 00 00 00
+T 00 00 C9
+R 00 00 00 00
diff --git a/sw/z80/drivers/build/ctc.sym b/sw/z80/drivers/build/ctc.sym
new file mode 100644
index 0000000..82ca00e
--- /dev/null
+++ b/sw/z80/drivers/build/ctc.sym
@@ -0,0 +1,27 @@
+ ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180), page 1.
+Hexadecimal [16-Bits]
+
+Symbol Table
+
+ .__.$$$. = 2710 L
+ .__.ABS. = 0000 G
+ .__.CPU. = 0000 L
+ .__.H$L. = 0000 L
+ 0 _ctc_control 0000 GR
+
+
+ ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180), page 2.
+Hexadecimal [16-Bits]
+
+Area Table
+
+ 0 _CODE size 1 flags 0
+ 1 _DATA size 0 flags 0
+ 2 _INITIALIZED size 0 flags 0
+ 3 _DABS size 0 flags 8
+ 4 _HOME size 0 flags 0
+ 5 _GSINIT size 0 flags 0
+ 6 _GSFINAL size 0 flags 0
+ 7 _INITIALIZER size 0 flags 0
+ 8 _CABS size 0 flags 8
+
diff --git a/sw/z80/drivers/build/pio.asm b/sw/z80/drivers/build/pio.asm
new file mode 100644
index 0000000..3045492
--- /dev/null
+++ b/sw/z80/drivers/build/pio.asm
@@ -0,0 +1,234 @@
+;--------------------------------------------------------
+; File Created by SDCC : free open source ANSI-C Compiler
+; Version 3.6.0 #9615 (Linux)
+;--------------------------------------------------------
+ .module pio
+ .optsdcc -mz80
+
+;--------------------------------------------------------
+; Public variables in this module
+;--------------------------------------------------------
+ .globl __pio_data
+ .globl __pio_control
+ .globl _pio_set_mode
+ .globl _pio_set_interrupts
+ .globl _pio_set_interrupts_mask
+ .globl _pio_read
+ .globl _pio_write
+;--------------------------------------------------------
+; special function registers
+;--------------------------------------------------------
+;--------------------------------------------------------
+; ram data
+;--------------------------------------------------------
+ .area _DATA
+;--------------------------------------------------------
+; ram data
+;--------------------------------------------------------
+ .area _INITIALIZED
+_pio_port:
+ .ds 2
+_pio_ctrl:
+ .ds 2
+;--------------------------------------------------------
+; absolute external ram data
+;--------------------------------------------------------
+ .area _DABS (ABS)
+;--------------------------------------------------------
+; global & static initialisations
+;--------------------------------------------------------
+ .area _HOME
+ .area _GSINIT
+ .area _GSFINAL
+ .area _GSINIT
+;--------------------------------------------------------
+; Home
+;--------------------------------------------------------
+ .area _HOME
+ .area _HOME
+;--------------------------------------------------------
+; code
+;--------------------------------------------------------
+ .area _CODE
+;pio.c:6: inline void _pio_data(int port, uint8_t data)
+; ---------------------------------
+; Function _pio_data
+; ---------------------------------
+__pio_data::
+;pio.c:8: *(pio_port + port) = data;
+ ld hl,#2
+ add hl,sp
+ ld iy,#_pio_port
+ ld a,0 (iy)
+ add a, (hl)
+ ld c,a
+ ld a,1 (iy)
+ inc hl
+ adc a, (hl)
+ ld b,a
+ ld hl, #4+0
+ add hl, sp
+ ld a, (hl)
+ ld (bc),a
+ ret
+;pio.c:11: inline void _pio_control(int port, uint8_t cmd)
+; ---------------------------------
+; Function _pio_control
+; ---------------------------------
+__pio_control::
+;pio.c:13: *(pio_ctrl + port) = cmd;
+ ld hl,#2
+ add hl,sp
+ ld iy,#_pio_ctrl
+ ld a,0 (iy)
+ add a, (hl)
+ ld c,a
+ ld a,1 (iy)
+ inc hl
+ adc a, (hl)
+ ld b,a
+ ld hl, #4+0
+ add hl, sp
+ ld a, (hl)
+ ld (bc),a
+ ret
+;pio.c:16: void pio_set_mode(int port, int mode, uint8_t io)
+; ---------------------------------
+; Function pio_set_mode
+; ---------------------------------
+_pio_set_mode::
+;pio.c:19: _pio_control(port, ((mode << 6) | 0x0F));
+ ld hl, #4+0
+ add hl, sp
+ ld a, (hl)
+ rrca
+ rrca
+ and a,#0xc0
+ or a, #0x0f
+ ld c,a
+ pop de
+ pop hl
+ push hl
+ push de
+;pio.c:13: *(pio_ctrl + port) = cmd;
+ ld iy,(_pio_ctrl)
+ ld e, l
+ ld d, h
+ add iy, de
+ ld 0 (iy), c
+;pio.c:23: if (mode == PIO_MODE_BIT_IO) {
+ ld iy,#4
+ add iy,sp
+ ld a,0 (iy)
+ sub a, #0x03
+ ret NZ
+ ld a,1 (iy)
+ or a, a
+ ret NZ
+;pio.c:24: _pio_control(port, io);
+ ld iy,#6
+ add iy,sp
+ ld c,0 (iy)
+;pio.c:13: *(pio_ctrl + port) = cmd;
+ ld de,(_pio_ctrl)
+ add hl,de
+ ld (hl),c
+;pio.c:24: _pio_control(port, io);
+ ret
+;pio.c:28: void pio_set_interrupts(int port, int control)
+; ---------------------------------
+; Function pio_set_interrupts
+; ---------------------------------
+_pio_set_interrupts::
+;pio.c:31: _pio_control(port, (control | 0x07));
+ ld hl, #4+0
+ add hl, sp
+ ld a, (hl)
+ or a, #0x07
+ ld c,a
+ pop de
+ pop hl
+ push hl
+ push de
+;pio.c:13: *(pio_ctrl + port) = cmd;
+ ld de,(_pio_ctrl)
+ add hl,de
+ ld (hl),c
+;pio.c:31: _pio_control(port, (control | 0x07));
+ ret
+;pio.c:34: void pio_set_interrupts_mask(int port, int control, uint8_t mask)
+; ---------------------------------
+; Function pio_set_interrupts_mask
+; ---------------------------------
+_pio_set_interrupts_mask::
+;pio.c:38: _pio_control(port, (control | 0x17));
+ ld hl, #4+0
+ add hl, sp
+ ld a, (hl)
+ or a, #0x17
+ ld c,a
+ pop de
+ pop hl
+ push hl
+ push de
+;pio.c:13: *(pio_ctrl + port) = cmd;
+ ld iy,(_pio_ctrl)
+ ld e, l
+ ld d, h
+ add iy, de
+ ld 0 (iy), c
+;pio.c:39: _pio_control(port, mask);
+ ld iy,#6
+ add iy,sp
+ ld c,0 (iy)
+;pio.c:13: *(pio_ctrl + port) = cmd;
+ ld de,(_pio_ctrl)
+ add hl,de
+ ld (hl),c
+;pio.c:39: _pio_control(port, mask);
+ ret
+;pio.c:42: uint8_t pio_read(int port)
+; ---------------------------------
+; Function pio_read
+; ---------------------------------
+_pio_read::
+;pio.c:44: return *(pio_port + port);
+ ld hl,#2
+ add hl,sp
+ ld iy,#_pio_port
+ ld a,0 (iy)
+ add a, (hl)
+ ld c,a
+ ld a,1 (iy)
+ inc hl
+ adc a, (hl)
+ ld b,a
+ ld a,(bc)
+ ld l,a
+ ret
+;pio.c:47: void pio_write(int port, uint8_t data)
+; ---------------------------------
+; Function pio_write
+; ---------------------------------
+_pio_write::
+;pio.c:49: _pio_data(port, data);
+ ld hl, #4+0
+ add hl, sp
+ ld c, (hl)
+ pop de
+ pop hl
+ push hl
+ push de
+;pio.c:8: *(pio_port + port) = data;
+ ld de,(_pio_port)
+ add hl,de
+ ld (hl),c
+;pio.c:49: _pio_data(port, data);
+ ret
+ .area _CODE
+ .area _INITIALIZER
+__xinit__pio_port:
+ .dw #0x4200
+__xinit__pio_ctrl:
+ .dw #0x4202
+ .area _CABS (ABS)
diff --git a/sw/z80/drivers/build/pio.lst b/sw/z80/drivers/build/pio.lst
new file mode 100644
index 0000000..0b83616
--- /dev/null
+++ b/sw/z80/drivers/build/pio.lst
@@ -0,0 +1,234 @@
+ 1 ;--------------------------------------------------------
+ 2 ; File Created by SDCC : free open source ANSI-C Compiler
+ 3 ; Version 3.6.0 #9615 (Linux)
+ 4 ;--------------------------------------------------------
+ 5 .module pio
+ 6 .optsdcc -mz80
+ 7
+ 8 ;--------------------------------------------------------
+ 9 ; Public variables in this module
+ 10 ;--------------------------------------------------------
+ 11 .globl __pio_data
+ 12 .globl __pio_control
+ 13 .globl _pio_set_mode
+ 14 .globl _pio_set_interrupts
+ 15 .globl _pio_set_interrupts_mask
+ 16 .globl _pio_read
+ 17 .globl _pio_write
+ 18 ;--------------------------------------------------------
+ 19 ; special function registers
+ 20 ;--------------------------------------------------------
+ 21 ;--------------------------------------------------------
+ 22 ; ram data
+ 23 ;--------------------------------------------------------
+ 24 .area _DATA
+ 25 ;--------------------------------------------------------
+ 26 ; ram data
+ 27 ;--------------------------------------------------------
+ 28 .area _INITIALIZED
+ 0000 29 _pio_port:
+ 0000 30 .ds 2
+ 0002 31 _pio_ctrl:
+ 0002 32 .ds 2
+ 33 ;--------------------------------------------------------
+ 34 ; absolute external ram data
+ 35 ;--------------------------------------------------------
+ 36 .area _DABS (ABS)
+ 37 ;--------------------------------------------------------
+ 38 ; global & static initialisations
+ 39 ;--------------------------------------------------------
+ 40 .area _HOME
+ 41 .area _GSINIT
+ 42 .area _GSFINAL
+ 43 .area _GSINIT
+ 44 ;--------------------------------------------------------
+ 45 ; Home
+ 46 ;--------------------------------------------------------
+ 47 .area _HOME
+ 48 .area _HOME
+ 49 ;--------------------------------------------------------
+ 50 ; code
+ 51 ;--------------------------------------------------------
+ 52 .area _CODE
+ 53 ;pio.c:6: inline void _pio_data(int port, uint8_t data)
+ 54 ; ---------------------------------
+ 55 ; Function _pio_data
+ 56 ; ---------------------------------
+ 0000 57 __pio_data::
+ 58 ;pio.c:8: *(pio_port + port) = data;
+ 0000 21 02 00 [10] 59 ld hl,#2
+ 0003 39 [11] 60 add hl,sp
+ 0004 FD 21r00r00 [14] 61 ld iy,#_pio_port
+ 0008 FD 7E 00 [19] 62 ld a,0 (iy)
+ 000B 86 [ 7] 63 add a, (hl)
+ 000C 4F [ 4] 64 ld c,a
+ 000D FD 7E 01 [19] 65 ld a,1 (iy)
+ 0010 23 [ 6] 66 inc hl
+ 0011 8E [ 7] 67 adc a, (hl)
+ 0012 47 [ 4] 68 ld b,a
+ 0013 21 04 00 [10] 69 ld hl, #4+0
+ 0016 39 [11] 70 add hl, sp
+ 0017 7E [ 7] 71 ld a, (hl)
+ 0018 02 [ 7] 72 ld (bc),a
+ 0019 C9 [10] 73 ret
+ 74 ;pio.c:11: inline void _pio_control(int port, uint8_t cmd)
+ 75 ; ---------------------------------
+ 76 ; Function _pio_control
+ 77 ; ---------------------------------
+ 001A 78 __pio_control::
+ 79 ;pio.c:13: *(pio_ctrl + port) = cmd;
+ 001A 21 02 00 [10] 80 ld hl,#2
+ 001D 39 [11] 81 add hl,sp
+ 001E FD 21r02r00 [14] 82 ld iy,#_pio_ctrl
+ 0022 FD 7E 00 [19] 83 ld a,0 (iy)
+ 0025 86 [ 7] 84 add a, (hl)
+ 0026 4F [ 4] 85 ld c,a
+ 0027 FD 7E 01 [19] 86 ld a,1 (iy)
+ 002A 23 [ 6] 87 inc hl
+ 002B 8E [ 7] 88 adc a, (hl)
+ 002C 47 [ 4] 89 ld b,a
+ 002D 21 04 00 [10] 90 ld hl, #4+0
+ 0030 39 [11] 91 add hl, sp
+ 0031 7E [ 7] 92 ld a, (hl)
+ 0032 02 [ 7] 93 ld (bc),a
+ 0033 C9 [10] 94 ret
+ 95 ;pio.c:16: void pio_set_mode(int port, int mode, uint8_t io)
+ 96 ; ---------------------------------
+ 97 ; Function pio_set_mode
+ 98 ; ---------------------------------
+ 0034 99 _pio_set_mode::
+ 100 ;pio.c:19: _pio_control(port, ((mode << 6) | 0x0F));
+ 0034 21 04 00 [10] 101 ld hl, #4+0
+ 0037 39 [11] 102 add hl, sp
+ 0038 7E [ 7] 103 ld a, (hl)
+ 0039 0F [ 4] 104 rrca
+ 003A 0F [ 4] 105 rrca
+ 003B E6 C0 [ 7] 106 and a,#0xc0
+ 003D F6 0F [ 7] 107 or a, #0x0f
+ 003F 4F [ 4] 108 ld c,a
+ 0040 D1 [10] 109 pop de
+ 0041 E1 [10] 110 pop hl
+ 0042 E5 [11] 111 push hl
+ 0043 D5 [11] 112 push de
+ 113 ;pio.c:13: *(pio_ctrl + port) = cmd;
+ 0044 FD 2Ar02r00 [20] 114 ld iy,(_pio_ctrl)
+ 0048 5D [ 4] 115 ld e, l
+ 0049 54 [ 4] 116 ld d, h
+ 004A FD 19 [15] 117 add iy, de
+ 004C FD 71 00 [19] 118 ld 0 (iy), c
+ 119 ;pio.c:23: if (mode == PIO_MODE_BIT_IO) {
+ 004F FD 21 04 00 [14] 120 ld iy,#4
+ 0053 FD 39 [15] 121 add iy,sp
+ 0055 FD 7E 00 [19] 122 ld a,0 (iy)
+ 0058 D6 03 [ 7] 123 sub a, #0x03
+ 005A C0 [11] 124 ret NZ
+ 005B FD 7E 01 [19] 125 ld a,1 (iy)
+ 005E B7 [ 4] 126 or a, a
+ 005F C0 [11] 127 ret NZ
+ 128 ;pio.c:24: _pio_control(port, io);
+ 0060 FD 21 06 00 [14] 129 ld iy,#6
+ 0064 FD 39 [15] 130 add iy,sp
+ 0066 FD 4E 00 [19] 131 ld c,0 (iy)
+ 132 ;pio.c:13: *(pio_ctrl + port) = cmd;
+ 0069 ED 5Br02r00 [20] 133 ld de,(_pio_ctrl)
+ 006D 19 [11] 134 add hl,de
+ 006E 71 [ 7] 135 ld (hl),c
+ 136 ;pio.c:24: _pio_control(port, io);
+ 006F C9 [10] 137 ret
+ 138 ;pio.c:28: void pio_set_interrupts(int port, int control)
+ 139 ; ---------------------------------
+ 140 ; Function pio_set_interrupts
+ 141 ; ---------------------------------
+ 0070 142 _pio_set_interrupts::
+ 143 ;pio.c:31: _pio_control(port, (control | 0x07));
+ 0070 21 04 00 [10] 144 ld hl, #4+0
+ 0073 39 [11] 145 add hl, sp
+ 0074 7E [ 7] 146 ld a, (hl)
+ 0075 F6 07 [ 7] 147 or a, #0x07
+ 0077 4F [ 4] 148 ld c,a
+ 0078 D1 [10] 149 pop de
+ 0079 E1 [10] 150 pop hl
+ 007A E5 [11] 151 push hl
+ 007B D5 [11] 152 push de
+ 153 ;pio.c:13: *(pio_ctrl + port) = cmd;
+ 007C ED 5Br02r00 [20] 154 ld de,(_pio_ctrl)
+ 0080 19 [11] 155 add hl,de
+ 0081 71 [ 7] 156 ld (hl),c
+ 157 ;pio.c:31: _pio_control(port, (control | 0x07));
+ 0082 C9 [10] 158 ret
+ 159 ;pio.c:34: void pio_set_interrupts_mask(int port, int control, uint8_t mask)
+ 160 ; ---------------------------------
+ 161 ; Function pio_set_interrupts_mask
+ 162 ; ---------------------------------
+ 0083 163 _pio_set_interrupts_mask::
+ 164 ;pio.c:38: _pio_control(port, (control | 0x17));
+ 0083 21 04 00 [10] 165 ld hl, #4+0
+ 0086 39 [11] 166 add hl, sp
+ 0087 7E [ 7] 167 ld a, (hl)
+ 0088 F6 17 [ 7] 168 or a, #0x17
+ 008A 4F [ 4] 169 ld c,a
+ 008B D1 [10] 170 pop de
+ 008C E1 [10] 171 pop hl
+ 008D E5 [11] 172 push hl
+ 008E D5 [11] 173 push de
+ 174 ;pio.c:13: *(pio_ctrl + port) = cmd;
+ 008F FD 2Ar02r00 [20] 175 ld iy,(_pio_ctrl)
+ 0093 5D [ 4] 176 ld e, l
+ 0094 54 [ 4] 177 ld d, h
+ 0095 FD 19 [15] 178 add iy, de
+ 0097 FD 71 00 [19] 179 ld 0 (iy), c
+ 180 ;pio.c:39: _pio_control(port, mask);
+ 009A FD 21 06 00 [14] 181 ld iy,#6
+ 009E FD 39 [15] 182 add iy,sp
+ 00A0 FD 4E 00 [19] 183 ld c,0 (iy)
+ 184 ;pio.c:13: *(pio_ctrl + port) = cmd;
+ 00A3 ED 5Br02r00 [20] 185 ld de,(_pio_ctrl)
+ 00A7 19 [11] 186 add hl,de
+ 00A8 71 [ 7] 187 ld (hl),c
+ 188 ;pio.c:39: _pio_control(port, mask);
+ 00A9 C9 [10] 189 ret
+ 190 ;pio.c:42: uint8_t pio_read(int port)
+ 191 ; ---------------------------------
+ 192 ; Function pio_read
+ 193 ; ---------------------------------
+ 00AA 194 _pio_read::
+ 195 ;pio.c:44: return *(pio_port + port);
+ 00AA 21 02 00 [10] 196 ld hl,#2
+ 00AD 39 [11] 197 add hl,sp
+ 00AE FD 21r00r00 [14] 198 ld iy,#_pio_port
+ 00B2 FD 7E 00 [19] 199 ld a,0 (iy)
+ 00B5 86 [ 7] 200 add a, (hl)
+ 00B6 4F [ 4] 201 ld c,a
+ 00B7 FD 7E 01 [19] 202 ld a,1 (iy)
+ 00BA 23 [ 6] 203 inc hl
+ 00BB 8E [ 7] 204 adc a, (hl)
+ 00BC 47 [ 4] 205 ld b,a
+ 00BD 0A [ 7] 206 ld a,(bc)
+ 00BE 6F [ 4] 207 ld l,a
+ 00BF C9 [10] 208 ret
+ 209 ;pio.c:47: void pio_write(int port, uint8_t data)
+ 210 ; ---------------------------------
+ 211 ; Function pio_write
+ 212 ; ---------------------------------
+ 00C0 213 _pio_write::
+ 214 ;pio.c:49: _pio_data(port, data);
+ 00C0 21 04 00 [10] 215 ld hl, #4+0
+ 00C3 39 [11] 216 add hl, sp
+ 00C4 4E [ 7] 217 ld c, (hl)
+ 00C5 D1 [10] 218 pop de
+ 00C6 E1 [10] 219 pop hl
+ 00C7 E5 [11] 220 push hl
+ 00C8 D5 [11] 221 push de
+ 222 ;pio.c:8: *(pio_port + port) = data;
+ 00C9 ED 5Br00r00 [20] 223 ld de,(_pio_port)
+ 00CD 19 [11] 224 add hl,de
+ 00CE 71 [ 7] 225 ld (hl),c
+ 226 ;pio.c:49: _pio_data(port, data);
+ 00CF C9 [10] 227 ret
+ 228 .area _CODE
+ 229 .area _INITIALIZER
+ 0000 230 __xinit__pio_port:
+ 0000 00 42 231 .dw #0x4200
+ 0002 232 __xinit__pio_ctrl:
+ 0002 02 42 233 .dw #0x4202
+ 234 .area _CABS (ABS)
diff --git a/sw/z80/drivers/build/pio.rel b/sw/z80/drivers/build/pio.rel
new file mode 100644
index 0000000..d9b1ac3
--- /dev/null
+++ b/sw/z80/drivers/build/pio.rel
@@ -0,0 +1,87 @@
+XL2
+H 9 areas 8 global symbols
+M pio
+O -mz80
+S .__.ABS. Def0000
+A _CODE size D0 flags 0 addr 0
+S _pio_set_interrupts Def0070
+S _pio_set_mode Def0034
+S _pio_set_interrupts_mask Def0083
+S _pio_read Def00AA
+S __pio_control Def001A
+S _pio_write Def00C0
+S __pio_data Def0000
+A _DATA size 0 flags 0 addr 0
+A _INITIALIZED size 4 flags 0 addr 0
+A _DABS size 0 flags 8 addr 0
+A _HOME size 0 flags 0 addr 0
+A _GSINIT size 0 flags 0 addr 0
+A _GSFINAL size 0 flags 0 addr 0
+A _INITIALIZER size 4 flags 0 addr 0
+A _CABS size 0 flags 8 addr 0
+T 00 00
+R 00 00 02 00
+T 00 00
+R 00 00 02 00
+T 02 00
+R 00 00 02 00
+T 02 00
+R 00 00 02 00
+T 00 00
+R 00 00 00 00
+T 00 00 21 02 00 39 FD 21 00 00 FD 7E 00 86 4F FD
+R 00 00 00 00 00 08 02 00
+T 0E 00 7E 01 23 8E 47 21 04 00 39 7E 02 C9
+R 00 00 00 00
+T 1A 00
+R 00 00 00 00
+T 1A 00 21 02 00 39 FD 21 02 00 FD 7E 00 86 4F FD
+R 00 00 00 00 00 08 02 00
+T 28 00 7E 01 23 8E 47 21 04 00 39 7E 02 C9
+R 00 00 00 00
+T 34 00
+R 00 00 00 00
+T 34 00 21 04 00 39 7E 0F 0F E6 C0 F6 0F 4F D1 E1
+R 00 00 00 00
+T 42 00 E5 D5 FD 2A 02 00 5D 54 FD 19 FD 71 00 FD
+R 00 00 00 00 00 06 02 00
+T 50 00 21 04 00 FD 39 FD 7E 00 D6 03 C0 FD 7E 01
+R 00 00 00 00
+T 5E 00 B7 C0 FD 21 06 00 FD 39 FD 4E 00 ED 5B
+R 00 00 00 00
+T 6B 00 02 00 19 71 C9
+R 00 00 00 00 00 02 02 00
+T 70 00
+R 00 00 00 00
+T 70 00 21 04 00 39 7E F6 07 4F D1 E1 E5 D5 ED 5B
+R 00 00 00 00
+T 7E 00 02 00 19 71 C9
+R 00 00 00 00 00 02 02 00
+T 83 00
+R 00 00 00 00
+T 83 00 21 04 00 39 7E F6 17 4F D1 E1 E5 D5 FD 2A
+R 00 00 00 00
+T 91 00 02 00 5D 54 FD 19 FD 71 00 FD 21 06 00 FD
+R 00 00 00 00 00 02 02 00
+T 9F 00 39 FD 4E 00 ED 5B 02 00 19 71 C9
+R 00 00 00 00 00 08 02 00
+T AA 00
+R 00 00 00 00
+T AA 00 21 02 00 39 FD 21 00 00 FD 7E 00 86 4F FD
+R 00 00 00 00 00 08 02 00
+T B8 00 7E 01 23 8E 47 0A 6F C9
+R 00 00 00 00
+T C0 00
+R 00 00 00 00
+T C0 00 21 04 00 39 4E D1 E1 E5 D5 ED 5B 00 00 19
+R 00 00 00 00 00 0D 02 00
+T CE 00 71 C9
+R 00 00 00 00
+T 00 00
+R 00 00 07 00
+T 00 00 00 42
+R 00 00 07 00
+T 02 00
+R 00 00 07 00
+T 02 00 02 42
+R 00 00 07 00
diff --git a/sw/z80/drivers/build/pio.sym b/sw/z80/drivers/build/pio.sym
new file mode 100644
index 0000000..52f787c
--- /dev/null
+++ b/sw/z80/drivers/build/pio.sym
@@ -0,0 +1,36 @@
+ ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180), page 1.
+Hexadecimal [16-Bits]
+
+Symbol Table
+
+ .__.$$$. = 2710 L
+ .__.ABS. = 0000 G
+ .__.CPU. = 0000 L
+ .__.H$L. = 0000 L
+ 0 __pio_control 001A GR
+ 0 __pio_data 0000 GR
+ 7 __xinit__pio_ctrl 0002 R
+ 7 __xinit__pio_port 0000 R
+ 2 _pio_ctrl 0002 R
+ 2 _pio_port 0000 R
+ 0 _pio_read 00AA GR
+ 0 _pio_set_interrupts 0070 GR
+ 0 _pio_set_interrupts_mask 0083 GR
+ 0 _pio_set_mode 0034 GR
+ 0 _pio_write 00C0 GR
+
+ ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180), page 2.
+Hexadecimal [16-Bits]
+
+Area Table
+
+ 0 _CODE size D0 flags 0
+ 1 _DATA size 0 flags 0
+ 2 _INITIALIZED size 4 flags 0
+ 3 _DABS size 0 flags 8
+ 4 _HOME size 0 flags 0
+ 5 _GSINIT size 0 flags 0
+ 6 _GSFINAL size 0 flags 0
+ 7 _INITIALIZER size 4 flags 0
+ 8 _CABS size 0 flags 8
+
diff --git a/sw/z80/drivers/build/usart.asm b/sw/z80/drivers/build/usart.asm
new file mode 100644
index 0000000..fb65d62
--- /dev/null
+++ b/sw/z80/drivers/build/usart.asm
@@ -0,0 +1,440 @@
+;--------------------------------------------------------
+; File Created by SDCC : free open source ANSI-C Compiler
+; Version 3.6.0 #9615 (Linux)
+;--------------------------------------------------------
+ .module usart
+ .optsdcc -mz80
+
+;--------------------------------------------------------
+; Public variables in this module
+;--------------------------------------------------------
+ .globl _usart_word_length
+ .globl _usart_set_baudrate
+ .globl _usart_set_parity
+ .globl _usart_set_stop_bits
+ .globl _usart_set_autoflow
+ .globl _usart_init
+ .globl _usart_transmit
+ .globl _usart_receive
+ .globl _usart_write
+ .globl _usart_read
+;--------------------------------------------------------
+; special function registers
+;--------------------------------------------------------
+;--------------------------------------------------------
+; ram data
+;--------------------------------------------------------
+ .area _DATA
+;--------------------------------------------------------
+; ram data
+;--------------------------------------------------------
+ .area _INITIALIZED
+__usart:
+ .ds 2
+;--------------------------------------------------------
+; absolute external ram data
+;--------------------------------------------------------
+ .area _DABS (ABS)
+;--------------------------------------------------------
+; global & static initialisations
+;--------------------------------------------------------
+ .area _HOME
+ .area _GSINIT
+ .area _GSFINAL
+ .area _GSINIT
+;--------------------------------------------------------
+; Home
+;--------------------------------------------------------
+ .area _HOME
+ .area _HOME
+;--------------------------------------------------------
+; code
+;--------------------------------------------------------
+ .area _CODE
+;usart.c:5: void usart_set_baudrate(uint16_t baudrate)
+; ---------------------------------
+; Function usart_set_baudrate
+; ---------------------------------
+_usart_set_baudrate::
+ push ix
+ ld ix,#0
+ add ix,sp
+;usart.c:8: _usart->LCR.divisor_latch_access = 1;
+ ld hl,(__usart)
+ ld bc,#0x0004
+ add hl,bc
+ ld a,(hl)
+ or a,#0x80
+ ld (hl),a
+;usart.c:9: _usart->buffer = 0x00FF & baudrate; // LSBs
+ ld hl,(__usart)
+ ld c,4 (ix)
+ ld (hl),c
+;usart.c:10: memcpy(&_usart->IER, &(baudrate >>8), 1);
+ ld de,(__usart)
+ inc de
+ ld l,5 (ix)
+ ld h,#0x00
+ ld a, (hl)
+ ld (de), a
+;usart.c:12: _usart->LCR.divisor_latch_access = 0;
+ ld hl,(__usart)
+ ld bc,#0x0004
+ add hl,bc
+ ld a,(hl)
+ and a,#0x7f
+ ld (hl),a
+ pop ix
+ ret
+;usart.c:15: void usart_set_parity(int mode)
+; ---------------------------------
+; Function usart_set_parity
+; ---------------------------------
+_usart_set_parity::
+;usart.c:18: _usart->LCR.even_parity = 1;
+ ld hl,(__usart)
+ ld bc,#0x0004
+ add hl,bc
+;usart.c:17: if (mode == USART_PARITY_EVEN) {
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ dec a
+ jr NZ,00104$
+ ld a,1 (iy)
+ or a, a
+ jr NZ,00104$
+;usart.c:18: _usart->LCR.even_parity = 1;
+ ld a,(hl)
+ or a,#0x10
+ ld (hl),a
+ jr 00105$
+00104$:
+;usart.c:20: else if (mode == USART_PARITY_ODD) {
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ sub a, #0x02
+ jr NZ,00105$
+ ld a,1 (iy)
+ or a, a
+ jr NZ,00105$
+;usart.c:21: _usart->LCR.even_parity = 0;
+ ld a,(hl)
+ and a,#0xef
+ ld (hl),a
+00105$:
+;usart.c:24: _usart->LCR.parity = (mode == USART_PARITY_NONE) ? 0 : 1;
+ ld hl,(__usart)
+ ld bc,#0x0004
+ add hl,bc
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ rlca
+ rlca
+ rlca
+ and a,#0xf8
+ and a,#0x08
+ ld c,a
+ ld a,(hl)
+ and a,#0xf7
+ or a,c
+ ld (hl),a
+ ret
+;usart.c:27: void usart_set_stop_bits(int count)
+; ---------------------------------
+; Function usart_set_stop_bits
+; ---------------------------------
+_usart_set_stop_bits::
+;usart.c:29: _usart->LCR.stop_bits = (count == USART_STOP_BITS_1) ? 0 : 1;
+ ld bc,(__usart)
+ inc bc
+ inc bc
+ inc bc
+ inc bc
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ sub a, #0x0a
+ jr NZ,00103$
+ ld a,1 (iy)
+ or a, a
+ jr NZ,00103$
+ ld a,#0x01
+ jr 00104$
+00103$:
+ xor a,a
+00104$:
+ xor a, #0x01
+ add a, a
+ add a, a
+ and a,#0x04
+ ld l,a
+ ld a,(bc)
+ and a,#0xfb
+ or a,l
+ ld (bc),a
+ ret
+;usart.c:32: void usart_word_length(int length)
+; ---------------------------------
+; Function usart_word_length
+; ---------------------------------
+_usart_word_length::
+;usart.c:34: _usart->LCR.word_length = length;
+ ld hl,(__usart)
+ ld bc,#0x0004
+ add hl,bc
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ and a,#0x03
+ ld c,a
+ ld a,(hl)
+ and a,#0xfc
+ or a,c
+ ld (hl),a
+ ret
+;usart.c:37: void usart_set_autoflow(int mode)
+; ---------------------------------
+; Function usart_set_autoflow
+; ---------------------------------
+_usart_set_autoflow::
+;usart.c:39: _usart->MCR.autoflow = (mode == USART_AUTOFLOW_OFF) ? 0 : 1;
+ ld hl,(__usart)
+ ld bc,#0x000c
+ add hl,bc
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ and a,#0x01
+ ld c,a
+ ld a,(hl)
+ and a,#0xfe
+ or a,c
+ ld (hl),a
+;usart.c:40: _usart->MCR.data_terminal_ready = (mode == USART_AUTOFLOW_ALL);
+ ld hl,(__usart)
+ ld bc,#0x0005
+ add hl,bc
+ ld a,0 (iy)
+ sub a, #0x03
+ jr NZ,00103$
+ ld a,1 (iy)
+ or a, a
+ jr NZ,00103$
+ ld a,#0x01
+ jr 00104$
+00103$:
+ xor a,a
+00104$:
+ and a,#0x01
+ ld c,a
+ ld a,(hl)
+ and a,#0xfe
+ or a,c
+ ld (hl),a
+ ret
+;usart.c:43: inline void usart_init(uint16_t baudrate, int parity, int stop_bits)
+; ---------------------------------
+; Function usart_init
+; ---------------------------------
+_usart_init::
+;usart.c:45: usart_set_baudrate(baudrate);
+ pop bc
+ pop hl
+ push hl
+ push bc
+ push hl
+ call _usart_set_baudrate
+ pop af
+;usart.c:46: usart_set_parity(parity);
+ ld hl, #4
+ add hl, sp
+ ld c, (hl)
+ inc hl
+ ld b, (hl)
+ push bc
+ call _usart_set_parity
+ pop af
+;usart.c:47: usart_set_stop_bits(stop_bits);
+ ld hl, #6
+ add hl, sp
+ ld c, (hl)
+ inc hl
+ ld b, (hl)
+ push bc
+ call _usart_set_stop_bits
+;usart.c:48: usart_set_autoflow(USART_AUTOFLOW_OFF);
+ ld hl, #0x0000
+ ex (sp),hl
+ call _usart_set_autoflow
+ pop af
+ ret
+;usart.c:51: void usart_transmit(uint8_t data)
+; ---------------------------------
+; Function usart_transmit
+; ---------------------------------
+_usart_transmit::
+;usart.c:53: _usart->buffer = data;
+ ld hl,(__usart)
+ ld iy,#2
+ add iy,sp
+ ld a,0 (iy)
+ ld (hl),a
+;usart.c:54: while (_usart->LSR.transmitter_holder_empty == 0); // wait
+00101$:
+ ld hl,(__usart)
+ ld bc,#0x000d
+ add hl,bc
+ ld a,(hl)
+ rlca
+ rlca
+ rlca
+ jr NC,00101$
+ ret
+;usart.c:57: uint8_t usart_receive()
+; ---------------------------------
+; Function usart_receive
+; ---------------------------------
+_usart_receive::
+;usart.c:59: return _usart->buffer;
+ ld hl,(__usart)
+ ld l,(hl)
+ ret
+;usart.c:62: int usart_write(uint8_t *data, size_t size)
+; ---------------------------------
+; Function usart_write
+; ---------------------------------
+_usart_write::
+ push ix
+ ld ix,#0
+ add ix,sp
+ push af
+;usart.c:64: uint8_t *dp = data;
+ ld a,4 (ix)
+ ld -2 (ix),a
+ ld a,5 (ix)
+ ld -1 (ix),a
+;usart.c:66: while (size--) {
+ ld c,6 (ix)
+ ld b,7 (ix)
+00104$:
+ ld e, c
+ ld d, b
+ dec bc
+ ld a,d
+ or a,e
+ jr Z,00106$
+;usart.c:67: _usart->buffer = *(dp++);
+ ld de,(__usart)
+ pop hl
+ push hl
+ ld a,(hl)
+ inc -2 (ix)
+ jr NZ,00126$
+ inc -1 (ix)
+00126$:
+ ld (de),a
+;usart.c:68: while (_usart->LSR.transmitter_empty);
+00101$:
+ ld hl,(__usart)
+ ld de,#0x000d
+ add hl,de
+ ld a,(hl)
+ rlca
+ rlca
+ jr NC,00104$
+ jr 00101$
+00106$:
+;usart.c:72: return size;
+ ld l, c
+ ld h, b
+ ld sp, ix
+ pop ix
+ ret
+;usart.c:75: int usart_read(uint8_t *buffer, size_t count)
+; ---------------------------------
+; Function usart_read
+; ---------------------------------
+_usart_read::
+ push ix
+ ld ix,#0
+ add ix,sp
+ ld hl,#-6
+ add hl,sp
+ ld sp,hl
+;usart.c:77: uint8_t *bp = buffer;
+ ld a,4 (ix)
+ ld -4 (ix),a
+ ld a,5 (ix)
+ ld -3 (ix),a
+;usart.c:80: while (count--) {
+ ld c,6 (ix)
+ ld b,7 (ix)
+ ld hl,#0x0000
+ ex (sp), hl
+00105$:
+ ld e, c
+ ld d, b
+ dec bc
+ ld a,d
+ or a,e
+ jr Z,00107$
+;usart.c:81: *(bp++) = _usart->buffer;
+ ld hl,(__usart)
+ ld e,(hl)
+ ld l,-4 (ix)
+ ld h,-3 (ix)
+ ld (hl),e
+ inc -4 (ix)
+ jr NZ,00123$
+ inc -3 (ix)
+00123$:
+ ld de,(__usart)
+;usart.c:83: if (_usart->LSR.framing_error || _usart->LSR.parity_error) {
+ ld hl,#0x000d
+ add hl,de
+ ld -2 (ix),l
+ ld -1 (ix),h
+ ld l,-2 (ix)
+ ld h,-1 (ix)
+ ld a,(hl)
+ rrca
+ rrca
+ rrca
+ and a,#0x01
+ jr NZ,00101$
+ ld l,-2 (ix)
+ ld h,-1 (ix)
+ ld a,(hl)
+ rrca
+ rrca
+ and a,#0x01
+ jr Z,00102$
+00101$:
+;usart.c:84: bp--; // delete last byte (?)
+ ld l,-4 (ix)
+ ld h,-3 (ix)
+ dec hl
+ ld -4 (ix),l
+ ld -3 (ix),h
+ jr 00105$
+00102$:
+;usart.c:86: read_count++;
+ inc -6 (ix)
+ jr NZ,00105$
+ inc -5 (ix)
+ jr 00105$
+00107$:
+;usart.c:90: return read_count;
+ pop hl
+ push hl
+ ld sp, ix
+ pop ix
+ ret
+ .area _CODE
+ .area _INITIALIZER
+__xinit___usart:
+ .dw #0x4000
+ .area _CABS (ABS)
diff --git a/sw/z80/drivers/build/usart.lst b/sw/z80/drivers/build/usart.lst
new file mode 100644
index 0000000..65365fe
--- /dev/null
+++ b/sw/z80/drivers/build/usart.lst
@@ -0,0 +1,440 @@
+ 1 ;--------------------------------------------------------
+ 2 ; File Created by SDCC : free open source ANSI-C Compiler
+ 3 ; Version 3.6.0 #9615 (Linux)
+ 4 ;--------------------------------------------------------
+ 5 .module usart
+ 6 .optsdcc -mz80
+ 7
+ 8 ;--------------------------------------------------------
+ 9 ; Public variables in this module
+ 10 ;--------------------------------------------------------
+ 11 .globl _usart_word_length
+ 12 .globl _usart_set_baudrate
+ 13 .globl _usart_set_parity
+ 14 .globl _usart_set_stop_bits
+ 15 .globl _usart_set_autoflow
+ 16 .globl _usart_init
+ 17 .globl _usart_transmit
+ 18 .globl _usart_receive
+ 19 .globl _usart_write
+ 20 .globl _usart_read
+ 21 ;--------------------------------------------------------
+ 22 ; special function registers
+ 23 ;--------------------------------------------------------
+ 24 ;--------------------------------------------------------
+ 25 ; ram data
+ 26 ;--------------------------------------------------------
+ 27 .area _DATA
+ 28 ;--------------------------------------------------------
+ 29 ; ram data
+ 30 ;--------------------------------------------------------
+ 31 .area _INITIALIZED
+ 0000 32 __usart:
+ 0000 33 .ds 2
+ 34 ;--------------------------------------------------------
+ 35 ; absolute external ram data
+ 36 ;--------------------------------------------------------
+ 37 .area _DABS (ABS)
+ 38 ;--------------------------------------------------------
+ 39 ; global & static initialisations
+ 40 ;--------------------------------------------------------
+ 41 .area _HOME
+ 42 .area _GSINIT
+ 43 .area _GSFINAL
+ 44 .area _GSINIT
+ 45 ;--------------------------------------------------------
+ 46 ; Home
+ 47 ;--------------------------------------------------------
+ 48 .area _HOME
+ 49 .area _HOME
+ 50 ;--------------------------------------------------------
+ 51 ; code
+ 52 ;--------------------------------------------------------
+ 53 .area _CODE
+ 54 ;usart.c:5: void usart_set_baudrate(uint16_t baudrate)
+ 55 ; ---------------------------------
+ 56 ; Function usart_set_baudrate
+ 57 ; ---------------------------------
+ 0000 58 _usart_set_baudrate::
+ 0000 DD E5 [15] 59 push ix
+ 0002 DD 21 00 00 [14] 60 ld ix,#0
+ 0006 DD 39 [15] 61 add ix,sp
+ 62 ;usart.c:8: _usart->LCR.divisor_latch_access = 1;
+ 0008 2Ar00r00 [16] 63 ld hl,(__usart)
+ 000B 01 04 00 [10] 64 ld bc,#0x0004
+ 000E 09 [11] 65 add hl,bc
+ 000F 7E [ 7] 66 ld a,(hl)
+ 0010 F6 80 [ 7] 67 or a,#0x80
+ 0012 77 [ 7] 68 ld (hl),a
+ 69 ;usart.c:9: _usart->buffer = 0x00FF & baudrate; // LSBs
+ 0013 2Ar00r00 [16] 70 ld hl,(__usart)
+ 0016 DD 4E 04 [19] 71 ld c,4 (ix)
+ 0019 71 [ 7] 72 ld (hl),c
+ 73 ;usart.c:10: memcpy(&_usart->IER, &(baudrate >>8), 1);
+ 001A ED 5Br00r00 [20] 74 ld de,(__usart)
+ 001E 13 [ 6] 75 inc de
+ 001F DD 6E 05 [19] 76 ld l,5 (ix)
+ 0022 26 00 [ 7] 77 ld h,#0x00
+ 0024 7E [ 7] 78 ld a, (hl)
+ 0025 12 [ 7] 79 ld (de), a
+ 80 ;usart.c:12: _usart->LCR.divisor_latch_access = 0;
+ 0026 2Ar00r00 [16] 81 ld hl,(__usart)
+ 0029 01 04 00 [10] 82 ld bc,#0x0004
+ 002C 09 [11] 83 add hl,bc
+ 002D 7E [ 7] 84 ld a,(hl)
+ 002E E6 7F [ 7] 85 and a,#0x7f
+ 0030 77 [ 7] 86 ld (hl),a
+ 0031 DD E1 [14] 87 pop ix
+ 0033 C9 [10] 88 ret
+ 89 ;usart.c:15: void usart_set_parity(int mode)
+ 90 ; ---------------------------------
+ 91 ; Function usart_set_parity
+ 92 ; ---------------------------------
+ 0034 93 _usart_set_parity::
+ 94 ;usart.c:18: _usart->LCR.even_parity = 1;
+ 0034 2Ar00r00 [16] 95 ld hl,(__usart)
+ 0037 01 04 00 [10] 96 ld bc,#0x0004
+ 003A 09 [11] 97 add hl,bc
+ 98 ;usart.c:17: if (mode == USART_PARITY_EVEN) {
+ 003B FD 21 02 00 [14] 99 ld iy,#2
+ 003F FD 39 [15] 100 add iy,sp
+ 0041 FD 7E 00 [19] 101 ld a,0 (iy)
+ 0044 3D [ 4] 102 dec a
+ 0045 20 0C [12] 103 jr NZ,00104$
+ 0047 FD 7E 01 [19] 104 ld a,1 (iy)
+ 004A B7 [ 4] 105 or a, a
+ 004B 20 06 [12] 106 jr NZ,00104$
+ 107 ;usart.c:18: _usart->LCR.even_parity = 1;
+ 004D 7E [ 7] 108 ld a,(hl)
+ 004E F6 10 [ 7] 109 or a,#0x10
+ 0050 77 [ 7] 110 ld (hl),a
+ 0051 18 17 [12] 111 jr 00105$
+ 0053 112 00104$:
+ 113 ;usart.c:20: else if (mode == USART_PARITY_ODD) {
+ 0053 FD 21 02 00 [14] 114 ld iy,#2
+ 0057 FD 39 [15] 115 add iy,sp
+ 0059 FD 7E 00 [19] 116 ld a,0 (iy)
+ 005C D6 02 [ 7] 117 sub a, #0x02
+ 005E 20 0A [12] 118 jr NZ,00105$
+ 0060 FD 7E 01 [19] 119 ld a,1 (iy)
+ 0063 B7 [ 4] 120 or a, a
+ 0064 20 04 [12] 121 jr NZ,00105$
+ 122 ;usart.c:21: _usart->LCR.even_parity = 0;
+ 0066 7E [ 7] 123 ld a,(hl)
+ 0067 E6 EF [ 7] 124 and a,#0xef
+ 0069 77 [ 7] 125 ld (hl),a
+ 006A 126 00105$:
+ 127 ;usart.c:24: _usart->LCR.parity = (mode == USART_PARITY_NONE) ? 0 : 1;
+ 006A 2Ar00r00 [16] 128 ld hl,(__usart)
+ 006D 01 04 00 [10] 129 ld bc,#0x0004
+ 0070 09 [11] 130 add hl,bc
+ 0071 FD 21 02 00 [14] 131 ld iy,#2
+ 0075 FD 39 [15] 132 add iy,sp
+ 0077 FD 7E 00 [19] 133 ld a,0 (iy)
+ 007A 07 [ 4] 134 rlca
+ 007B 07 [ 4] 135 rlca
+ 007C 07 [ 4] 136 rlca
+ 007D E6 F8 [ 7] 137 and a,#0xf8
+ 007F E6 08 [ 7] 138 and a,#0x08
+ 0081 4F [ 4] 139 ld c,a
+ 0082 7E [ 7] 140 ld a,(hl)
+ 0083 E6 F7 [ 7] 141 and a,#0xf7
+ 0085 B1 [ 4] 142 or a,c
+ 0086 77 [ 7] 143 ld (hl),a
+ 0087 C9 [10] 144 ret
+ 145 ;usart.c:27: void usart_set_stop_bits(int count)
+ 146 ; ---------------------------------
+ 147 ; Function usart_set_stop_bits
+ 148 ; ---------------------------------
+ 0088 149 _usart_set_stop_bits::
+ 150 ;usart.c:29: _usart->LCR.stop_bits = (count == USART_STOP_BITS_1) ? 0 : 1;
+ 0088 ED 4Br00r00 [20] 151 ld bc,(__usart)
+ 008C 03 [ 6] 152 inc bc
+ 008D 03 [ 6] 153 inc bc
+ 008E 03 [ 6] 154 inc bc
+ 008F 03 [ 6] 155 inc bc
+ 0090 FD 21 02 00 [14] 156 ld iy,#2
+ 0094 FD 39 [15] 157 add iy,sp
+ 0096 FD 7E 00 [19] 158 ld a,0 (iy)
+ 0099 D6 0A [ 7] 159 sub a, #0x0a
+ 009B 20 0A [12] 160 jr NZ,00103$
+ 009D FD 7E 01 [19] 161 ld a,1 (iy)
+ 00A0 B7 [ 4] 162 or a, a
+ 00A1 20 04 [12] 163 jr NZ,00103$
+ 00A3 3E 01 [ 7] 164 ld a,#0x01
+ 00A5 18 01 [12] 165 jr 00104$
+ 00A7 166 00103$:
+ 00A7 AF [ 4] 167 xor a,a
+ 00A8 168 00104$:
+ 00A8 EE 01 [ 7] 169 xor a, #0x01
+ 00AA 87 [ 4] 170 add a, a
+ 00AB 87 [ 4] 171 add a, a
+ 00AC E6 04 [ 7] 172 and a,#0x04
+ 00AE 6F [ 4] 173 ld l,a
+ 00AF 0A [ 7] 174 ld a,(bc)
+ 00B0 E6 FB [ 7] 175 and a,#0xfb
+ 00B2 B5 [ 4] 176 or a,l
+ 00B3 02 [ 7] 177 ld (bc),a
+ 00B4 C9 [10] 178 ret
+ 179 ;usart.c:32: void usart_word_length(int length)
+ 180 ; ---------------------------------
+ 181 ; Function usart_word_length
+ 182 ; ---------------------------------
+ 00B5 183 _usart_word_length::
+ 184 ;usart.c:34: _usart->LCR.word_length = length;
+ 00B5 2Ar00r00 [16] 185 ld hl,(__usart)
+ 00B8 01 04 00 [10] 186 ld bc,#0x0004
+ 00BB 09 [11] 187 add hl,bc
+ 00BC FD 21 02 00 [14] 188 ld iy,#2
+ 00C0 FD 39 [15] 189 add iy,sp
+ 00C2 FD 7E 00 [19] 190 ld a,0 (iy)
+ 00C5 E6 03 [ 7] 191 and a,#0x03
+ 00C7 4F [ 4] 192 ld c,a
+ 00C8 7E [ 7] 193 ld a,(hl)
+ 00C9 E6 FC [ 7] 194 and a,#0xfc
+ 00CB B1 [ 4] 195 or a,c
+ 00CC 77 [ 7] 196 ld (hl),a
+ 00CD C9 [10] 197 ret
+ 198 ;usart.c:37: void usart_set_autoflow(int mode)
+ 199 ; ---------------------------------
+ 200 ; Function usart_set_autoflow
+ 201 ; ---------------------------------
+ 00CE 202 _usart_set_autoflow::
+ 203 ;usart.c:39: _usart->MCR.autoflow = (mode == USART_AUTOFLOW_OFF) ? 0 : 1;
+ 00CE 2Ar00r00 [16] 204 ld hl,(__usart)
+ 00D1 01 0C 00 [10] 205 ld bc,#0x000c
+ 00D4 09 [11] 206 add hl,bc
+ 00D5 FD 21 02 00 [14] 207 ld iy,#2
+ 00D9 FD 39 [15] 208 add iy,sp
+ 00DB FD 7E 00 [19] 209 ld a,0 (iy)
+ 00DE E6 01 [ 7] 210 and a,#0x01
+ 00E0 4F [ 4] 211 ld c,a
+ 00E1 7E [ 7] 212 ld a,(hl)
+ 00E2 E6 FE [ 7] 213 and a,#0xfe
+ 00E4 B1 [ 4] 214 or a,c
+ 00E5 77 [ 7] 215 ld (hl),a
+ 216 ;usart.c:40: _usart->MCR.data_terminal_ready = (mode == USART_AUTOFLOW_ALL);
+ 00E6 2Ar00r00 [16] 217 ld hl,(__usart)
+ 00E9 01 05 00 [10] 218 ld bc,#0x0005
+ 00EC 09 [11] 219 add hl,bc
+ 00ED FD 7E 00 [19] 220 ld a,0 (iy)
+ 00F0 D6 03 [ 7] 221 sub a, #0x03
+ 00F2 20 0A [12] 222 jr NZ,00103$
+ 00F4 FD 7E 01 [19] 223 ld a,1 (iy)
+ 00F7 B7 [ 4] 224 or a, a
+ 00F8 20 04 [12] 225 jr NZ,00103$
+ 00FA 3E 01 [ 7] 226 ld a,#0x01
+ 00FC 18 01 [12] 227 jr 00104$
+ 00FE 228 00103$:
+ 00FE AF [ 4] 229 xor a,a
+ 00FF 230 00104$:
+ 00FF E6 01 [ 7] 231 and a,#0x01
+ 0101 4F [ 4] 232 ld c,a
+ 0102 7E [ 7] 233 ld a,(hl)
+ 0103 E6 FE [ 7] 234 and a,#0xfe
+ 0105 B1 [ 4] 235 or a,c
+ 0106 77 [ 7] 236 ld (hl),a
+ 0107 C9 [10] 237 ret
+ 238 ;usart.c:43: inline void usart_init(uint16_t baudrate, int parity, int stop_bits)
+ 239 ; ---------------------------------
+ 240 ; Function usart_init
+ 241 ; ---------------------------------
+ 0108 242 _usart_init::
+ 243 ;usart.c:45: usart_set_baudrate(baudrate);
+ 0108 C1 [10] 244 pop bc
+ 0109 E1 [10] 245 pop hl
+ 010A E5 [11] 246 push hl
+ 010B C5 [11] 247 push bc
+ 010C E5 [11] 248 push hl
+ 010D CDr00r00 [17] 249 call _usart_set_baudrate
+ 0110 F1 [10] 250 pop af
+ 251 ;usart.c:46: usart_set_parity(parity);
+ 0111 21 04 00 [10] 252 ld hl, #4
+ 0114 39 [11] 253 add hl, sp
+ 0115 4E [ 7] 254 ld c, (hl)
+ 0116 23 [ 6] 255 inc hl
+ 0117 46 [ 7] 256 ld b, (hl)
+ 0118 C5 [11] 257 push bc
+ 0119 CDr34r00 [17] 258 call _usart_set_parity
+ 011C F1 [10] 259 pop af
+ 260 ;usart.c:47: usart_set_stop_bits(stop_bits);
+ 011D 21 06 00 [10] 261 ld hl, #6
+ 0120 39 [11] 262 add hl, sp
+ 0121 4E [ 7] 263 ld c, (hl)
+ 0122 23 [ 6] 264 inc hl
+ 0123 46 [ 7] 265 ld b, (hl)
+ 0124 C5 [11] 266 push bc
+ 0125 CDr88r00 [17] 267 call _usart_set_stop_bits
+ 268 ;usart.c:48: usart_set_autoflow(USART_AUTOFLOW_OFF);
+ 0128 21 00 00 [10] 269 ld hl, #0x0000
+ 012B E3 [19] 270 ex (sp),hl
+ 012C CDrCEr00 [17] 271 call _usart_set_autoflow
+ 012F F1 [10] 272 pop af
+ 0130 C9 [10] 273 ret
+ 274 ;usart.c:51: void usart_transmit(uint8_t data)
+ 275 ; ---------------------------------
+ 276 ; Function usart_transmit
+ 277 ; ---------------------------------
+ 0131 278 _usart_transmit::
+ 279 ;usart.c:53: _usart->buffer = data;
+ 0131 2Ar00r00 [16] 280 ld hl,(__usart)
+ 0134 FD 21 02 00 [14] 281 ld iy,#2
+ 0138 FD 39 [15] 282 add iy,sp
+ 013A FD 7E 00 [19] 283 ld a,0 (iy)
+ 013D 77 [ 7] 284 ld (hl),a
+ 285 ;usart.c:54: while (_usart->LSR.transmitter_holder_empty == 0); // wait
+ 013E 286 00101$:
+ 013E 2Ar00r00 [16] 287 ld hl,(__usart)
+ 0141 01 0D 00 [10] 288 ld bc,#0x000d
+ 0144 09 [11] 289 add hl,bc
+ 0145 7E [ 7] 290 ld a,(hl)
+ 0146 07 [ 4] 291 rlca
+ 0147 07 [ 4] 292 rlca
+ 0148 07 [ 4] 293 rlca
+ 0149 30 F3 [12] 294 jr NC,00101$
+ 014B C9 [10] 295 ret
+ 296 ;usart.c:57: uint8_t usart_receive()
+ 297 ; ---------------------------------
+ 298 ; Function usart_receive
+ 299 ; ---------------------------------
+ 014C 300 _usart_receive::
+ 301 ;usart.c:59: return _usart->buffer;
+ 014C 2Ar00r00 [16] 302 ld hl,(__usart)
+ 014F 6E [ 7] 303 ld l,(hl)
+ 0150 C9 [10] 304 ret
+ 305 ;usart.c:62: int usart_write(uint8_t *data, size_t size)
+ 306 ; ---------------------------------
+ 307 ; Function usart_write
+ 308 ; ---------------------------------
+ 0151 309 _usart_write::
+ 0151 DD E5 [15] 310 push ix
+ 0153 DD 21 00 00 [14] 311 ld ix,#0
+ 0157 DD 39 [15] 312 add ix,sp
+ 0159 F5 [11] 313 push af
+ 314 ;usart.c:64: uint8_t *dp = data;
+ 015A DD 7E 04 [19] 315 ld a,4 (ix)
+ 015D DD 77 FE [19] 316 ld -2 (ix),a
+ 0160 DD 7E 05 [19] 317 ld a,5 (ix)
+ 0163 DD 77 FF [19] 318 ld -1 (ix),a
+ 319 ;usart.c:66: while (size--) {
+ 0166 DD 4E 06 [19] 320 ld c,6 (ix)
+ 0169 DD 46 07 [19] 321 ld b,7 (ix)
+ 016C 322 00104$:
+ 016C 59 [ 4] 323 ld e, c
+ 016D 50 [ 4] 324 ld d, b
+ 016E 0B [ 6] 325 dec bc
+ 016F 7A [ 4] 326 ld a,d
+ 0170 B3 [ 4] 327 or a,e
+ 0171 28 1E [12] 328 jr Z,00106$
+ 329 ;usart.c:67: _usart->buffer = *(dp++);
+ 0173 ED 5Br00r00 [20] 330 ld de,(__usart)
+ 0177 E1 [10] 331 pop hl
+ 0178 E5 [11] 332 push hl
+ 0179 7E [ 7] 333 ld a,(hl)
+ 017A DD 34 FE [23] 334 inc -2 (ix)
+ 017D 20 03 [12] 335 jr NZ,00126$
+ 017F DD 34 FF [23] 336 inc -1 (ix)
+ 0182 337 00126$:
+ 0182 12 [ 7] 338 ld (de),a
+ 339 ;usart.c:68: while (_usart->LSR.transmitter_empty);
+ 0183 340 00101$:
+ 0183 2Ar00r00 [16] 341 ld hl,(__usart)
+ 0186 11 0D 00 [10] 342 ld de,#0x000d
+ 0189 19 [11] 343 add hl,de
+ 018A 7E [ 7] 344 ld a,(hl)
+ 018B 07 [ 4] 345 rlca
+ 018C 07 [ 4] 346 rlca
+ 018D 30 DD [12] 347 jr NC,00104$
+ 018F 18 F2 [12] 348 jr 00101$
+ 0191 349 00106$:
+ 350 ;usart.c:72: return size;
+ 0191 69 [ 4] 351 ld l, c
+ 0192 60 [ 4] 352 ld h, b
+ 0193 DD F9 [10] 353 ld sp, ix
+ 0195 DD E1 [14] 354 pop ix
+ 0197 C9 [10] 355 ret
+ 356 ;usart.c:75: int usart_read(uint8_t *buffer, size_t count)
+ 357 ; ---------------------------------
+ 358 ; Function usart_read
+ 359 ; ---------------------------------
+ 0198 360 _usart_read::
+ 0198 DD E5 [15] 361 push ix
+ 019A DD 21 00 00 [14] 362 ld ix,#0
+ 019E DD 39 [15] 363 add ix,sp
+ 01A0 21 FA FF [10] 364 ld hl,#-6
+ 01A3 39 [11] 365 add hl,sp
+ 01A4 F9 [ 6] 366 ld sp,hl
+ 367 ;usart.c:77: uint8_t *bp = buffer;
+ 01A5 DD 7E 04 [19] 368 ld a,4 (ix)
+ 01A8 DD 77 FC [19] 369 ld -4 (ix),a
+ 01AB DD 7E 05 [19] 370 ld a,5 (ix)
+ 01AE DD 77 FD [19] 371 ld -3 (ix),a
+ 372 ;usart.c:80: while (count--) {
+ 01B1 DD 4E 06 [19] 373 ld c,6 (ix)
+ 01B4 DD 46 07 [19] 374 ld b,7 (ix)
+ 01B7 21 00 00 [10] 375 ld hl,#0x0000
+ 01BA E3 [19] 376 ex (sp), hl
+ 01BB 377 00105$:
+ 01BB 59 [ 4] 378 ld e, c
+ 01BC 50 [ 4] 379 ld d, b
+ 01BD 0B [ 6] 380 dec bc
+ 01BE 7A [ 4] 381 ld a,d
+ 01BF B3 [ 4] 382 or a,e
+ 01C0 28 55 [12] 383 jr Z,00107$
+ 384 ;usart.c:81: *(bp++) = _usart->buffer;
+ 01C2 2Ar00r00 [16] 385 ld hl,(__usart)
+ 01C5 5E [ 7] 386 ld e,(hl)
+ 01C6 DD 6E FC [19] 387 ld l,-4 (ix)
+ 01C9 DD 66 FD [19] 388 ld h,-3 (ix)
+ 01CC 73 [ 7] 389 ld (hl),e
+ 01CD DD 34 FC [23] 390 inc -4 (ix)
+ 01D0 20 03 [12] 391 jr NZ,00123$
+ 01D2 DD 34 FD [23] 392 inc -3 (ix)
+ 01D5 393 00123$:
+ 01D5 ED 5Br00r00 [20] 394 ld de,(__usart)
+ 395 ;usart.c:83: if (_usart->LSR.framing_error || _usart->LSR.parity_error) {
+ 01D9 21 0D 00 [10] 396 ld hl,#0x000d
+ 01DC 19 [11] 397 add hl,de
+ 01DD DD 75 FE [19] 398 ld -2 (ix),l
+ 01E0 DD 74 FF [19] 399 ld -1 (ix),h
+ 01E3 DD 6E FE [19] 400 ld l,-2 (ix)
+ 01E6 DD 66 FF [19] 401 ld h,-1 (ix)
+ 01E9 7E [ 7] 402 ld a,(hl)
+ 01EA 0F [ 4] 403 rrca
+ 01EB 0F [ 4] 404 rrca
+ 01EC 0F [ 4] 405 rrca
+ 01ED E6 01 [ 7] 406 and a,#0x01
+ 01EF 20 0D [12] 407 jr NZ,00101$
+ 01F1 DD 6E FE [19] 408 ld l,-2 (ix)
+ 01F4 DD 66 FF [19] 409 ld h,-1 (ix)
+ 01F7 7E [ 7] 410 ld a,(hl)
+ 01F8 0F [ 4] 411 rrca
+ 01F9 0F [ 4] 412 rrca
+ 01FA E6 01 [ 7] 413 and a,#0x01
+ 01FC 28 0F [12] 414 jr Z,00102$
+ 01FE 415 00101$:
+ 416 ;usart.c:84: bp--; // delete last byte (?)
+ 01FE DD 6E FC [19] 417 ld l,-4 (ix)
+ 0201 DD 66 FD [19] 418 ld h,-3 (ix)
+ 0204 2B [ 6] 419 dec hl
+ 0205 DD 75 FC [19] 420 ld -4 (ix),l
+ 0208 DD 74 FD [19] 421 ld -3 (ix),h
+ 020B 18 AE [12] 422 jr 00105$
+ 020D 423 00102$:
+ 424 ;usart.c:86: read_count++;
+ 020D DD 34 FA [23] 425 inc -6 (ix)
+ 0210 20 A9 [12] 426 jr NZ,00105$
+ 0212 DD 34 FB [23] 427 inc -5 (ix)
+ 0215 18 A4 [12] 428 jr 00105$
+ 0217 429 00107$:
+ 430 ;usart.c:90: return read_count;
+ 0217 E1 [10] 431 pop hl
+ 0218 E5 [11] 432 push hl
+ 0219 DD F9 [10] 433 ld sp, ix
+ 021B DD E1 [14] 434 pop ix
+ 021D C9 [10] 435 ret
+ 436 .area _CODE
+ 437 .area _INITIALIZER
+ 0000 438 __xinit___usart:
+ 0000 00 40 439 .dw #0x4000
+ 440 .area _CABS (ABS)
diff --git a/sw/z80/drivers/build/usart.rel b/sw/z80/drivers/build/usart.rel
new file mode 100644
index 0000000..29ad600
--- /dev/null
+++ b/sw/z80/drivers/build/usart.rel
@@ -0,0 +1,184 @@
+XL2
+H 9 areas B global symbols
+M usart
+O -mz80
+S .__.ABS. Def0000
+A _CODE size 21E flags 0 addr 0
+S _usart_read Def0198
+S _usart_set_autoflow Def00CE
+S _usart_word_length Def00B5
+S _usart_receive Def014C
+S _usart_write Def0151
+S _usart_transmit Def0131
+S _usart_set_baudrate Def0000
+S _usart_init Def0108
+S _usart_set_stop_bits Def0088
+S _usart_set_parity Def0034
+A _DATA size 0 flags 0 addr 0
+A _INITIALIZED size 2 flags 0 addr 0
+A _DABS size 0 flags 8 addr 0
+A _HOME size 0 flags 0 addr 0
+A _GSINIT size 0 flags 0 addr 0
+A _GSFINAL size 0 flags 0 addr 0
+A _INITIALIZER size 2 flags 0 addr 0
+A _CABS size 0 flags 8 addr 0
+T 00 00
+R 00 00 02 00
+T 00 00
+R 00 00 02 00
+T 00 00
+R 00 00 00 00
+T 00 00 DD E5 DD 21 00 00 DD 39 2A 00 00 01 04 00
+R 00 00 00 00 00 0B 02 00
+T 0E 00 09 7E F6 80 77 2A 00 00 DD 4E 04 71 ED 5B
+R 00 00 00 00 00 08 02 00
+T 1C 00 00 00 13 DD 6E 05 26 00 7E 12 2A 00 00 01
+R 00 00 00 00 00 02 02 00 00 0D 02 00
+T 2A 00 04 00 09 7E E6 7F 77 DD E1 C9
+R 00 00 00 00
+T 34 00
+R 00 00 00 00
+T 34 00 2A 00 00 01 04 00 09 FD 21 02 00 FD 39 FD
+R 00 00 00 00 00 03 02 00
+T 42 00 7E 00 3D 20 0C FD 7E 01 B7 20 06 7E F6 10
+R 00 00 00 00
+T 50 00 77 18 17
+R 00 00 00 00
+T 53 00
+R 00 00 00 00
+T 53 00 FD 21 02 00 FD 39 FD 7E 00 D6 02 20 0A FD
+R 00 00 00 00
+T 61 00 7E 01 B7 20 04 7E E6 EF 77
+R 00 00 00 00
+T 6A 00
+R 00 00 00 00
+T 6A 00 2A 00 00 01 04 00 09 FD 21 02 00 FD 39 FD
+R 00 00 00 00 00 03 02 00
+T 78 00 7E 00 07 07 07 E6 F8 E6 08 4F 7E E6 F7 B1
+R 00 00 00 00
+T 86 00 77 C9
+R 00 00 00 00
+T 88 00
+R 00 00 00 00
+T 88 00 ED 4B 00 00 03 03 03 03 FD 21 02 00 FD 39
+R 00 00 00 00 00 04 02 00
+T 96 00 FD 7E 00 D6 0A 20 0A FD 7E 01 B7 20 04 3E
+R 00 00 00 00
+T A4 00 01 18 01
+R 00 00 00 00
+T A7 00
+R 00 00 00 00
+T A7 00 AF
+R 00 00 00 00
+T A8 00
+R 00 00 00 00
+T A8 00 EE 01 87 87 E6 04 6F 0A E6 FB B5 02 C9
+R 00 00 00 00
+T B5 00
+R 00 00 00 00
+T B5 00 2A 00 00 01 04 00 09 FD 21 02 00 FD 39 FD
+R 00 00 00 00 00 03 02 00
+T C3 00 7E 00 E6 03 4F 7E E6 FC B1 77 C9
+R 00 00 00 00
+T CE 00
+R 00 00 00 00
+T CE 00 2A 00 00 01 0C 00 09 FD 21 02 00 FD 39 FD
+R 00 00 00 00 00 03 02 00
+T DC 00 7E 00 E6 01 4F 7E E6 FE B1 77 2A 00 00 01
+R 00 00 00 00 00 0D 02 00
+T EA 00 05 00 09 FD 7E 00 D6 03 20 0A FD 7E 01 B7
+R 00 00 00 00
+T F8 00 20 04 3E 01 18 01
+R 00 00 00 00
+T FE 00
+R 00 00 00 00
+T FE 00 AF
+R 00 00 00 00
+T FF 00
+R 00 00 00 00
+T FF 00 E6 01 4F 7E E6 FE B1 77 C9
+R 00 00 00 00
+T 08 01
+R 00 00 00 00
+T 08 01 C1 E1 E5 C5 E5 CD 00 00 F1 21 04 00 39 4E
+R 00 00 00 00 00 08 00 00
+T 16 01 23 46 C5 CD 34 00 F1 21 06 00 39 4E 23 46
+R 00 00 00 00 00 06 00 00
+T 24 01 C5 CD 88 00 21 00 00 E3 CD CE 00 F1 C9
+R 00 00 00 00 00 04 00 00 00 0B 00 00
+T 31 01
+R 00 00 00 00
+T 31 01 2A 00 00 FD 21 02 00 FD 39 FD 7E 00 77
+R 00 00 00 00 00 03 02 00
+T 3E 01
+R 00 00 00 00
+T 3E 01 2A 00 00 01 0D 00 09 7E 07 07 07 30 F3 C9
+R 00 00 00 00 00 03 02 00
+T 4C 01
+R 00 00 00 00
+T 4C 01 2A 00 00 6E C9
+R 00 00 00 00 00 03 02 00
+T 51 01
+R 00 00 00 00
+T 51 01 DD E5 DD 21 00 00 DD 39 F5 DD 7E 04 DD 77
+R 00 00 00 00
+T 5F 01 FE DD 7E 05 DD 77 FF DD 4E 06 DD 46 07
+R 00 00 00 00
+T 6C 01
+R 00 00 00 00
+T 6C 01 59 50 0B 7A B3 28 1E ED 5B 00 00 E1 E5 7E
+R 00 00 00 00 00 0B 02 00
+T 7A 01 DD 34 FE 20 03 DD 34 FF
+R 00 00 00 00
+T 82 01
+R 00 00 00 00
+T 82 01 12
+R 00 00 00 00
+T 83 01
+R 00 00 00 00
+T 83 01 2A 00 00 11 0D 00 19 7E 07 07 30 DD 18 F2
+R 00 00 00 00 00 03 02 00
+T 91 01
+R 00 00 00 00
+T 91 01 69 60 DD F9 DD E1 C9
+R 00 00 00 00
+T 98 01
+R 00 00 00 00
+T 98 01 DD E5 DD 21 00 00 DD 39 21 FA FF 39 F9 DD
+R 00 00 00 00
+T A6 01 7E 04 DD 77 FC DD 7E 05 DD 77 FD DD 4E 06
+R 00 00 00 00
+T B4 01 DD 46 07 21 00 00 E3
+R 00 00 00 00
+T BB 01
+R 00 00 00 00
+T BB 01 59 50 0B 7A B3 28 55 2A 00 00 5E DD 6E FC
+R 00 00 00 00 00 0A 02 00
+T C9 01 DD 66 FD 73 DD 34 FC 20 03 DD 34 FD
+R 00 00 00 00
+T D5 01
+R 00 00 00 00
+T D5 01 ED 5B 00 00 21 0D 00 19 DD 75 FE DD 74 FF
+R 00 00 00 00 00 04 02 00
+T E3 01 DD 6E FE DD 66 FF 7E 0F 0F 0F E6 01 20 0D
+R 00 00 00 00
+T F1 01 DD 6E FE DD 66 FF 7E 0F 0F E6 01 28 0F
+R 00 00 00 00
+T FE 01
+R 00 00 00 00
+T FE 01 DD 6E FC DD 66 FD 2B DD 75 FC DD 74 FD 18
+R 00 00 00 00
+T 0C 02 AE
+R 00 00 00 00
+T 0D 02
+R 00 00 00 00
+T 0D 02 DD 34 FA 20 A9 DD 34 FB 18 A4
+R 00 00 00 00
+T 17 02
+R 00 00 00 00
+T 17 02 E1 E5 DD F9 DD E1 C9
+R 00 00 00 00
+T 00 00
+R 00 00 07 00
+T 00 00 00 40
+R 00 00 07 00
diff --git a/sw/z80/drivers/build/usart.sym b/sw/z80/drivers/build/usart.sym
new file mode 100644
index 0000000..71004e3
--- /dev/null
+++ b/sw/z80/drivers/build/usart.sym
@@ -0,0 +1,38 @@
+ ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180), page 1.
+Hexadecimal [16-Bits]
+
+Symbol Table
+
+ .__.$$$. = 2710 L
+ .__.ABS. = 0000 G
+ .__.CPU. = 0000 L
+ .__.H$L. = 0000 L
+ 2 __usart 0000 R
+ 7 __xinit___usart 0000 R
+ 0 _usart_init 0108 GR
+ 0 _usart_read 0198 GR
+ 0 _usart_receive 014C GR
+ 0 _usart_set_autoflow 00CE GR
+ 0 _usart_set_baudrate 0000 GR
+ 0 _usart_set_parity 0034 GR
+ 0 _usart_set_stop_bits 0088 GR
+ 0 _usart_transmit 0131 GR
+ 0 _usart_word_length 00B5 GR
+ 0 _usart_write 0151 GR
+
+
+ ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180), page 2.
+Hexadecimal [16-Bits]
+
+Area Table
+
+ 0 _CODE size 21E flags 0
+ 1 _DATA size 0 flags 0
+ 2 _INITIALIZED size 2 flags 0
+ 3 _DABS size 0 flags 8
+ 4 _HOME size 0 flags 0
+ 5 _GSINIT size 0 flags 0
+ 6 _GSFINAL size 0 flags 0
+ 7 _INITIALIZER size 2 flags 0
+ 8 _CABS size 0 flags 8
+
generated by cgit v1.2.1 (git 2.18.0) at 2024-12-24 04:19:10 +0100