summaryrefslogtreecommitdiffstats
path: root/hw/History (follow)
Commit message (Expand)AuthorAgeFilesLines
* board complete, generate gerber (x2) fileshardwareNao Pross2017-05-2349-0/+0
* finish wiring and add eurocard compliant standard holesNao Pross2017-05-19161-0/+0
* wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2017-05-1950-0/+0
* new traces for cpu signals and for high address to the MMU / addr decoderNao Pross2017-05-1825-0/+0
* wiring for CTC (U8) to address bus and data busNao Pross2017-05-1815-0/+0
* wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross2017-05-184-0/+0
* wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2017-05-1830-0/+0
* created new layout (starting over)Nao Pross2017-05-0958-0/+0
* complete wiring for serial interface connector and logicNao Pross2017-05-0584-0/+0
* add switches datasheets for footprintsNao Pross2017-05-055-0/+0
* start printed circuit board designNao Pross2017-04-28123-0/+0
* scheme update and PCB startNao Pross2017-04-1337-0/+0
* schematic completeNao Pross2017-04-04112-0/+0
* added iospace address decoderNao Pross2017-03-3110-0/+0
* changed scheme layoutNao Pross2017-03-23104-0/+0
* hardware nearly finishedNao Pross2017-03-17324-0/+0
* hw: moved everything to one sheetNao Pross2017-03-06215-0/+0
* hw: created library project, doc: added 74LS193 datasheetNao Pross2017-02-2412-0/+0
* hw: created sch, doc: added uart datasheetNao Pross2017-02-241-0/+0
* hw: created z80acpu in sch libraryNao Pross2017-02-1410-0/+0
generated by cgit v1.2.1 (git 2.18.0) at 2024-12-22 21:00:32 +0100