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* board complete, generate gerber (x2) fileshardwareNao Pross2017-05-2349-0/+0
| | | | | this is probably the last commit before printing the PCB, unless there are some other errors in the board design
* finish wiring and add eurocard compliant standard holesNao Pross2017-05-19161-0/+0
| | | | | | since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused).
* wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2017-05-1950-0/+0
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* new traces for cpu signals and for high address to the MMU / addr decoderNao Pross2017-05-1825-0/+0
| | | | there are also many other minor changes to connect various wires
* wiring for CTC (U8) to address bus and data busNao Pross2017-05-1815-0/+0
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* wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross2017-05-184-0/+0
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* wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2017-05-1830-0/+0
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* created new layout (starting over)Nao Pross2017-05-0958-0/+0
| | | | the old layout is still under hw/MainBoard1.PcbDoc
* complete wiring for serial interface connector and logicNao Pross2017-05-0584-0/+0
| | | | | | | other changes: - new layout, probably the board will have to be resized to a nonstandard size (currently 2EUROCARD) - new footprint HDR5x2_SOCKET for standard 5x2 flatcable connectors
* add switches datasheets for footprintsNao Pross2017-05-055-0/+0
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* start printed circuit board designNao Pross2017-04-28123-0/+0
| | | | | | | | | wired: - clock circiuts - reset button set layout for: - CPU & memory - serial interface
* scheme update and PCB startNao Pross2017-04-1337-0/+0
| | | | | | add missing capacitor and resistor values (serial XTAL) create new eurocard standard compliant PCB for the uPC and other minor fixes
* schematic completeNao Pross2017-04-04112-0/+0
| | | | | | hw: change address decoder chip from GAL16V8 to M4-32/32 (CPLD) change main bus connector with a custom one (intead of PC/104) start building footprint library
* added iospace address decoderNao Pross2017-03-3110-0/+0
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* changed scheme layoutNao Pross2017-03-23104-0/+0
| | | | | | | | | hw: changed scheme and annotated components doc: added build script for windows sw: added res/ folder with blaster and created jedec document for address decoder pld
* hardware nearly finishedNao Pross2017-03-17324-0/+0
| | | | | | | | | | | | | doc: added datasheets for - GAL16V8 - MAX214 - MAX232 added script to build doc under windows with miktex updated notes hw: finished i/o devices and bus viewer sw: created files for pld programming
* hw: moved everything to one sheetNao Pross2017-03-06215-0/+0
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* hw: created library project, doc: added 74LS193 datasheetNao Pross2017-02-2412-0/+0
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* hw: created sch, doc: added uart datasheetNao Pross2017-02-241-0/+0
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* hw: created z80acpu in sch libraryNao Pross2017-02-1410-0/+0