summaryrefslogtreecommitdiffstats
path: root/hw/__Previews (follow)
Commit message (Expand)AuthorAgeFilesLines
* board complete, generate gerber (x2) fileshardwareNao Pross2017-05-235-21/+21
* finish wiring and add eurocard compliant standard holesNao Pross2017-05-194-12/+12
* wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2017-05-192-6/+6
* new traces for cpu signals and for high address to the MMU / addr decoderNao Pross2017-05-181-3/+3
* wiring for CTC (U8) to address bus and data busNao Pross2017-05-181-3/+3
* wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross2017-05-181-3/+3
* wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2017-05-182-6/+6
* created new layout (starting over)Nao Pross2017-05-096-15/+29
* complete wiring for serial interface connector and logicNao Pross2017-05-055-15/+15
* add switches datasheets for footprintsNao Pross2017-05-055-15/+15
* start printed circuit board designNao Pross2017-04-285-24/+24
* scheme update and PCB startNao Pross2017-04-135-12/+26
* schematic completeNao Pross2017-04-046-12/+40
* added iospace address decoderNao Pross2017-03-314-12/+12
* changed scheme layoutNao Pross2017-03-234-12/+12
* hardware nearly finishedNao Pross2017-03-175-12/+54
* hw: moved everything to one sheetNao Pross2017-03-062-9/+23
* doc: added L7805ACV datasheet; hw: updated schemeNao Pross2017-03-051-3/+3
* hw: created library project, doc: added 74LS193 datasheetNao Pross2017-02-241-3/+3
* hw: created sch, doc: added uart datasheetNao Pross2017-02-241-0/+14
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-18 06:19:00 +0200