summaryrefslogtreecommitdiffstats
path: root/hw (follow)
Commit message (Expand)AuthorAgeFilesLines
* new traces for cpu signals and for high address to the MMU / addr decoderNao Pross2017-05-1827-3/+3
* wiring for CTC (U8) to address bus and data busNao Pross2017-05-1817-3/+3
* wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross2017-05-186-3/+3
* wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2017-05-1833-6/+6
* created new layout (starting over)Nao Pross2017-05-0973-130/+1039
* complete wiring for serial interface connector and logicNao Pross2017-05-0597-15/+20
* add switches datasheets for footprintsNao Pross2017-05-0513-17/+17
* start printed circuit board designNao Pross2017-04-28158-31/+11374
* scheme update and PCB startNao Pross2017-04-1351-109/+1787
* schematic completeNao Pross2017-04-04131-98/+214
* added iospace address decoderNao Pross2017-03-3117-12/+12
* changed scheme layoutNao Pross2017-03-23119-13/+189
* hardware nearly finishedNao Pross2017-03-17339-125/+850
* hw: moved everything to one sheetNao Pross2017-03-06226-57/+662
* doc: added L7805ACV datasheet; hw: updated schemeNao Pross2017-03-056-13/+1275
* hw: created library project, doc: added 74LS193 datasheetNao Pross2017-02-2417-464/+5
* hw: created sch, doc: added uart datasheetNao Pross2017-02-245-3/+501
* hw: created z80acpu in sch libraryNao Pross2017-02-1412-0/+1005
generated by cgit v1.2.1 (git 2.18.0) at 2024-12-23 02:06:54 +0100