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|
|--------------------------------------------|
|- ispDesignExpert Fitter Report File -|
|- Version 8.3.02.12_DE_HDL_BASE -|
|- (c)Copyright, Lattice Semiconductor 1999 -|
|--------------------------------------------|
Start: Thu Nov 23 11:55:45 2017
End : Thu Nov 23 11:55:45 2017 $$$ Elapsed time: 00:00:00
===========================================================================
Part [C:\ISPTOOLS\ISPSYS/dat/mach4/mach432] Design [address_decoder.tt4]
* Place/Route options (keycode = 540674)
= Spread Placement: ON
= No. Routing Attempts/Placement 2
* Placement Completion
+- Block +------- IO Pins Available
| +- Macrocells Available | +-- IO Pins Used
| | +- Signals to Place | | +----- Logic Array Inputs
| | | +- Placed | | | +- Array Inputs Used
_|____|____|____|_______________|____|_____________|___|________________
0 | 16 | 0 | 0 => n/a | 16 | 10 => 62% | 33 | 0 => 0%
1 | 16 | 10 | 10 => 100% | 16 | 11 => 68% | 33 | 11 => 33%
---|----|----|------------|-------|------------|-----|------------------
| Avg number of array inputs in used blocks : 11.00 => 33%
* Input/Clock Signal count: 11 -> placed: 11 = 100%
Resources Available Used
-----------------------------------------------------------------
Input Pins : 0 0 => 0%
I/O Pins : 32 21 => 65%
Clock Only Pins : 0 0 => 0%
Clock/Input Pins : 2 0 => 0%
Logic Blocks : 2 1 => 50%
Macrocells : 32 10 => 31%
PT Clusters : 32 0 => 0%
- Single PT Clusters : 32 10 => 31%
Input Registers : 0
* Routing Completion: 100%
* Attempts: Place [ 21] Route [ 0]
===========================================================================
Signal Fanout Table
===========================================================================
+- Signal Number
| +- Block Location ('+' for dedicated inputs)
| | +- Sig Type
| | | +- Signal-to-Pin Assignment
| | | | Fanout to Logic Blocks Signal Name
___|__|__|____|____________________________________________________________
1| 1|OUT| 28|=> ..| CSCTC
2| 1|OUT| 29|=> ..| CSPIO
3| 1|OUT| 26|=> ..| CSRAM
4| 1|OUT| 25|=> ..| CSROMH
5| 1|OUT| 24|=> ..| CSROML
6| 1|OUT| 27|=> ..| CSUART
7| 1|INP| 30|=> .1| IORQ
8| 0|INP| 18|=> .1| MMU_IN_12_
9| 0|INP| 19|=> .1| MMU_IN_13_
10| 0|INP| 20|=> .1| MMU_IN_14_
11| 0|INP| 21|=> .1| MMU_IN_15_
12| 0|INP| 7|=> .1| MMU_IN_2_
13| 0|INP| 6|=> .1| MMU_IN_3_
14| 0|INP| 5|=> .1| MMU_IN_4_
15| 0|INP| 4|=> .1| MMU_IN_5_
16| 0|INP| 3|=> .1| MMU_IN_6_
17| 0|INP| 2|=> .1| MMU_IN_7_
18| 1|OUT| 39|=> ..| MMU_OUT_12_
19| 1|OUT| 38|=> ..| MMU_OUT_13_
20| 1|OUT| 37|=> ..| MMU_OUT_14_
21| 1|OUT| 36|=> ..| MMU_OUT_15_
---------------------------------------------------------------------------
===========================================================================
< C:\ISPTOOLS\ISPSYS/dat/mach4/mach432 Device Pin Assignments >
===========================================================================
+- Device Pin No
| Pin Type +- Signal Fixed (*)
| | | Signal Name
____|_____|_________|______________________________________________________
1 | GND | | | (pwr/test)
2 | I_O | 0_07|*| MMU_IN_7_
3 | I_O | 0_06|*| MMU_IN_6_
4 | I_O | 0_05|*| MMU_IN_5_
5 | I_O | 0_04|*| MMU_IN_4_
6 | I_O | 0_03|*| MMU_IN_3_
7 | I_O | 0_02|*| MMU_IN_2_
8 | I_O | 0_01| | -
9 | I_O | 0_00| | -
10 | JTAG | | | (pwr/test)
11 | CkIn | | | -
12 | GND | | | (pwr/test)
13 | JTAG | | | (pwr/test)
14 | I_O | 0_08| | -
15 | I_O | 0_09| | -
16 | I_O | 0_10| | -
17 | I_O | 0_11| | -
18 | I_O | 0_12|*| MMU_IN_12_
19 | I_O | 0_13|*| MMU_IN_13_
20 | I_O | 0_14|*| MMU_IN_14_
21 | I_O | 0_15|*| MMU_IN_15_
22 | Vcc | | | (pwr/test)
23 | GND | | | (pwr/test)
24 | I_O | 1_15|*| CSROML
25 | I_O | 1_14|*| CSROMH
26 | I_O | 1_13|*| CSRAM
27 | I_O | 1_12|*| CSUART
28 | I_O | 1_11|*| CSCTC
29 | I_O | 1_10|*| CSPIO
30 | I_O | 1_09|*| IORQ
31 | I_O | 1_08| | -
32 | JTAG | | | (pwr/test)
33 | CkIn | | | -
34 | GND | | | (pwr/test)
35 | JTAG | | | (pwr/test)
36 | I_O | 1_00|*| MMU_OUT_15_
37 | I_O | 1_01|*| MMU_OUT_14_
38 | I_O | 1_02|*| MMU_OUT_13_
39 | I_O | 1_03|*| MMU_OUT_12_
40 | I_O | 1_04| | -
41 | I_O | 1_05| | -
42 | I_O | 1_06| | -
43 | I_O | 1_07| | -
44 | Vcc | | | (pwr/test)
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| | | | 9| => | 0 1 2 3 4 5 6 7
1| | | | 8| => | 1 2 3 4 5 6 7 0
2| MMU_IN_2_|INP|*| 7| => | 2 3 4 5 6 7 0 1
3| MMU_IN_3_|INP|*| 6| => | 3 4 5 6 7 0 1 2
4| MMU_IN_4_|INP|*| 5| => | 4 5 6 7 0 1 2 3
5| MMU_IN_5_|INP|*| 4| => | 5 6 7 0 1 2 3 4
6| MMU_IN_6_|INP|*| 3| => | 6 7 0 1 2 3 4 5
7| MMU_IN_7_|INP|*| 2| => | 7 0 1 2 3 4 5 6
8| | | | 14| => | 8 9 10 11 12 13 14 15
9| | | | 15| => | 9 10 11 12 13 14 15 8
10| | | | 16| => | 10 11 12 13 14 15 8 9
11| | | | 17| => | 11 12 13 14 15 8 9 10
12| MMU_IN_12_|INP|*| 18| => | 12 13 14 15 8 9 10 11
13| MMU_IN_13_|INP|*| 19| => | 13 14 15 8 9 10 11 12
14| MMU_IN_14_|INP|*| 20| => | 14 15 8 9 10 11 12 13
15| MMU_IN_15_|INP|*| 21| => | 15 8 9 10 11 12 13 14
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| | | | 9| => | Input macrocell [ -]
1| | | | 8| => | Input macrocell [ -]
2| MMU_IN_2_|INP|*| 7| => | Input macrocell [ -]
3| MMU_IN_3_|INP|*| 6| => | Input macrocell [ -]
4| MMU_IN_4_|INP|*| 5| => | Input macrocell [ -]
5| MMU_IN_5_|INP|*| 4| => | Input macrocell [ -]
6| MMU_IN_6_|INP|*| 3| => | Input macrocell [ -]
7| MMU_IN_7_|INP|*| 2| => | Input macrocell [ -]
8| | | | 14| => | Input macrocell [ -]
9| | | | 15| => | Input macrocell [ -]
10| | | | 16| => | Input macrocell [ -]
11| | | | 17| => | Input macrocell [ -]
12| MMU_IN_12_|INP|*| 18| => | Input macrocell [ -]
13| MMU_IN_13_|INP|*| 19| => | Input macrocell [ -]
14| MMU_IN_14_|INP|*| 20| => | Input macrocell [ -]
15| MMU_IN_15_|INP|*| 21| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 9| -| | ]
[MCell 0 | 45| -| | ]
1 [IOpin 1 | 8| -| | ]
[MCell 1 | 46| -| | ]
2 [IOpin 2 | 7|INP MMU_IN_2_|*|*]
[MCell 2 | 47| -| | ]
3 [IOpin 3 | 6|INP MMU_IN_3_|*|*]
[MCell 3 | 48| -| | ]
4 [IOpin 4 | 5|INP MMU_IN_4_|*|*]
[MCell 4 | 49| -| | ]
5 [IOpin 5 | 4|INP MMU_IN_5_|*|*]
[MCell 5 | 50| -| | ]
6 [IOpin 6 | 3|INP MMU_IN_6_|*|*]
[MCell 6 | 51| -| | ]
7 [IOpin 7 | 2|INP MMU_IN_7_|*|*]
[MCell 7 | 52| -| | ]
8 [IOpin 8 | 14| -| | ]
[MCell 8 | 53| -| | ]
9 [IOpin 9 | 15| -| | ]
[MCell 9 | 54| -| | ]
10 [IOpin 10 | 16| -| | ]
[MCell 10 | 55| -| | ]
11 [IOpin 11 | 17| -| | ]
[MCell 11 | 56| -| | ]
12 [IOpin 12 | 18|INP MMU_IN_12_|*|*]
[MCell 12 | 57| -| | ]
13 [IOpin 13 | 19|INP MMU_IN_13_|*|*]
[MCell 13 | 58| -| | ]
14 [IOpin 14 | 20|INP MMU_IN_14_|*|*]
[MCell 14 | 59| -| | ]
15 [IOpin 15 | 21|INP MMU_IN_15_|*|*]
[MCell 15 | 60| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| MMU_OUT_12_|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
1| MMU_OUT_14_|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| MMU_OUT_13_|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig
5| MMU_OUT_15_|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| CSPIO|OUT| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
9| CSUART|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig
10| CSROMH|OUT| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig
11| | ? | | S | | 4 free | 1 XOR free
12| CSCTC|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
13| CSRAM|OUT| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig
14| CSROML|OUT| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| MMU_OUT_12_|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
1| MMU_OUT_14_|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
2| | ? | | S | |=> can support up to [ 18] logic PT(s)
3| | ? | | S | |=> can support up to [ 18] logic PT(s)
4| MMU_OUT_13_|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
5| MMU_OUT_15_|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
6| | ? | | S | |=> can support up to [ 14] logic PT(s)
7| | ? | | S | |=> can support up to [ 10] logic PT(s)
8| CSPIO|OUT| | S | 1 |=> can support up to [ 13] logic PT(s)
9| CSUART|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
10| CSROMH|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
11| | ? | | S | |=> can support up to [ 17] logic PT(s)
12| CSCTC|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
13| CSRAM|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
14| CSROML|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
15| | ? | | S | |=> can support up to [ 9] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 1] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| MMU_OUT_12_|OUT| | => | 0 1 2 ( 3) 4 5 6 7 | 36 37 38 ( 39) 40 41 42 43
1| MMU_OUT_14_|OUT| | => | 0 ( 1) 2 3 4 5 6 7 | 36 ( 37) 38 39 40 41 42 43
2| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
3| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
4| MMU_OUT_13_|OUT| | => | 0 1 ( 2) 3 4 5 6 7 | 36 37 ( 38) 39 40 41 42 43
5| MMU_OUT_15_|OUT| | => |( 0) 1 2 3 4 5 6 7 |( 36) 37 38 39 40 41 42 43
6| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
7| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
8| CSPIO|OUT| | => | 8 9 ( 10) 11 12 13 14 15 | 31 30 ( 29) 28 27 26 25 24
9| CSUART|OUT| | => | 8 9 10 11 ( 12) 13 14 15 | 31 30 29 28 ( 27) 26 25 24
10| CSROMH|OUT| | => | 8 9 10 11 12 13 ( 14) 15 | 31 30 29 28 27 26 ( 25) 24
11| | | | => | 8 9 10 11 12 13 14 15 | 31 30 29 28 27 26 25 24
12| CSCTC|OUT| | => | 8 9 10 ( 11) 12 13 14 15 | 31 30 29 ( 28) 27 26 25 24
13| CSRAM|OUT| | => | 8 9 10 11 12 ( 13) 14 15 | 31 30 29 28 27 ( 26) 25 24
14| CSROML|OUT| | => | 8 9 10 11 12 13 14 ( 15)| 31 30 29 28 27 26 25 ( 24)
15| | | | => | 8 9 10 11 12 13 14 15 | 31 30 29 28 27 26 25 24
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| MMU_OUT_15_|OUT|*| 36| => | 0 1 2 3 4 ( 5) 6 7
1| MMU_OUT_14_|OUT|*| 37| => | ( 1) 2 3 4 5 6 7 0
2| MMU_OUT_13_|OUT|*| 38| => | 2 3 ( 4) 5 6 7 0 1
3| MMU_OUT_12_|OUT|*| 39| => | 3 4 5 6 7 ( 0) 1 2
4| | | | 40| => | 4 5 6 7 0 1 2 3
5| | | | 41| => | 5 6 7 0 1 2 3 4
6| | | | 42| => | 6 7 0 1 2 3 4 5
7| | | | 43| => | 7 0 1 2 3 4 5 6
8| | | | 31| => | 8 9 10 11 12 13 14 15
9| IORQ|INP|*| 30| => | 9 10 11 12 13 14 15 8
10| CSPIO|OUT|*| 29| => | 10 11 12 13 14 15 ( 8) 9
11| CSCTC|OUT|*| 28| => | 11 (12) 13 14 15 8 9 10
12| CSUART|OUT|*| 27| => | 12 13 14 15 8 ( 9) 10 11
13| CSRAM|OUT|*| 26| => | (13) 14 15 8 9 10 11 12
14| CSROMH|OUT|*| 25| => | 14 15 8 9 (10) 11 12 13
15| CSROML|OUT|*| 24| => | 15 8 9 10 11 12 13 (14)
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| MMU_OUT_15_|OUT|*| 36| => | Input macrocell [ -]
1| MMU_OUT_14_|OUT|*| 37| => | Input macrocell [ -]
2| MMU_OUT_13_|OUT|*| 38| => | Input macrocell [ -]
3| MMU_OUT_12_|OUT|*| 39| => | Input macrocell [ -]
4| | | | 40| => | Input macrocell [ -]
5| | | | 41| => | Input macrocell [ -]
6| | | | 42| => | Input macrocell [ -]
7| | | | 43| => | Input macrocell [ -]
8| | | | 31| => | Input macrocell [ -]
9| IORQ|INP|*| 30| => | Input macrocell [ -]
10| CSPIO|OUT|*| 29| => | Input macrocell [ -]
11| CSCTC|OUT|*| 28| => | Input macrocell [ -]
12| CSUART|OUT|*| 27| => | Input macrocell [ -]
13| CSRAM|OUT|*| 26| => | Input macrocell [ -]
14| CSROMH|OUT|*| 25| => | Input macrocell [ -]
15| CSROML|OUT|*| 24| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 36|OUT MMU_OUT_15_|*| ]
[MCell 0 | 61|OUT MMU_OUT_12_| | ]
1 [IOpin 1 | 37|OUT MMU_OUT_14_|*| ]
[MCell 1 | 62|OUT MMU_OUT_14_| | ]
2 [IOpin 2 | 38|OUT MMU_OUT_13_|*| ]
[MCell 2 | 63| -| | ]
3 [IOpin 3 | 39|OUT MMU_OUT_12_|*| ]
[MCell 3 | 64| -| | ]
4 [IOpin 4 | 40| -| | ]
[MCell 4 | 65|OUT MMU_OUT_13_| | ]
5 [IOpin 5 | 41| -| | ]
[MCell 5 | 66|OUT MMU_OUT_15_| | ]
6 [IOpin 6 | 42| -| | ]
[MCell 6 | 67| -| | ]
7 [IOpin 7 | 43| -| | ]
[MCell 7 | 68| -| | ]
8 [IOpin 8 | 31| -| | ]
[MCell 8 | 69|OUT CSPIO| | ]
9 [IOpin 9 | 30|INP IORQ|*|*]
[MCell 9 | 70|OUT CSUART| | ]
10 [IOpin 10 | 29|OUT CSPIO|*| ]
[MCell 10 | 71|OUT CSROMH| | ]
11 [IOpin 11 | 28|OUT CSCTC|*| ]
[MCell 11 | 72| -| | ]
12 [IOpin 12 | 27|OUT CSUART|*| ]
[MCell 12 | 73|OUT CSCTC| | ]
13 [IOpin 13 | 26|OUT CSRAM|*| ]
[MCell 13 | 74|OUT CSRAM| | ]
14 [IOpin 14 | 25|OUT CSROMH|*| ]
[MCell 14 | 75|OUT CSROML| | ]
15 [IOpin 15 | 24|OUT CSROML|*| ]
[MCell 15 | 76| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| IOPin 0 7 ( 2)| MMU_IN_7_
Mux01| IOPin 0 4 ( 5)| MMU_IN_4_
Mux02| ... | ...
Mux03| ... | ...
Mux04| ... | ...
Mux05| ... | ...
Mux06| IOPin 0 6 ( 3)| MMU_IN_6_
Mux07| IOPin 0 3 ( 6)| MMU_IN_3_
Mux08| IOPin 0 15 ( 21)| MMU_IN_15_
Mux09| IOPin 0 5 ( 4)| MMU_IN_5_
Mux10| IOPin 0 12 ( 18)| MMU_IN_12_
Mux11| ... | ...
Mux12| IOPin 0 13 ( 19)| MMU_IN_13_
Mux13| IOPin 1 9 ( 30)| IORQ
Mux14| ... | ...
Mux15| IOPin 0 14 ( 20)| MMU_IN_14_
Mux16| ... | ...
Mux17| ... | ...
Mux18| IOPin 0 2 ( 7)| MMU_IN_2_
Mux19| ... | ...
Mux20| ... | ...
Mux21| ... | ...
Mux22| ... | ...
Mux23| ... | ...
Mux24| ... | ...
Mux25| ... | ...
Mux26| ... | ...
Mux27| ... | ...
Mux28| ... | ...
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
Mux32| ... | ...
---------------------------------------------------------------------------
|
